AI Data Centers and Their Appetite for Power Semiconductors
AI data center power demand and semiconductors: why accelerator racks changed the architecture, what higher DC voltage does to losses, and what is uncertain.
Updated: October 27, 2026
Read AI data-center power growth as a planning input for topology and capacity—not as a precise forecast you can enter into an MRP system. Third-party market figures vary by scope; translate them into engineering actions: voltage class mix, package capacity, and lead-time risk.
For device-level follow-ups see power semiconductor market outlook 2026–2030 and silicon carbide market 2026.
| Market signal | Engineering response | Do not |
|---|---|---|
| Demand growth in a segment | Stress-test second sources and MoQ | Scale unique MPNs prematurely |
| Shift to higher V / WBG | Revisit derating and gate-drive | Copy Si designs unchanged |
| Regional capacity headlines | Map real lead times by package | Treat press CAGR as bookings |
| Efficiency regulation pressure | Budget conduction + switching loss | Optimize only sticker VF |
Why AI changes rack power
A conventional server rack holds a number of general-purpose machines whose combined draw was, for a long time, modest enough that the electrical distribution inside the hall was not a design problem. An accelerator-dense rack concentrates far more computation into the same volume, and therefore draws far more current through the same physical space. Current, not voltage, is what sizes the copper, and it is also what turns distribution loss into a serious number.
The comparison that helps is water in a pipe. Doubling the flow through a fixed pipe roughly doubles the pressure drop at a given speed, but the friction loss rises with the square of the flow, so lines have to grow quickly or the losses become unacceptable. In electrical distribution the same relationship applies to current: loss rises with the square of current for a fixed resistance, which is the reason a higher distribution voltage is attractive, because the same power at a higher voltage means a lower current.
From 12 V to 48 V to DC distribution
A traditional server distribution bus inside the rack is a low voltage, historically 12 V, chosen because it is safe to work with and because the loads were small. As rack power rose, the current at that voltage rose with it, and the copper and the loss became the constraint. Moving the rack bus to 48 V reduces the current by a factor of four for the same power, and it has become a common design in high-density computing for that reason.
The next step in the same direction is distributing direct current at a higher voltage into the hall or to the rack, with a conversion stage placed close to the load. This is not new engineering — telecommunications facilities have distributed direct current for decades, and electric vehicles use high-voltage direct current buses — but it is a change from the alternating-current distribution that data centres inherited from general building practice. The trade is that conversion moves closer to the load, and a conversion stage has a cost, a loss and a failure rate of its own.
| Approach | What it buys | What it costs |
|---|---|---|
| Low-voltage rack bus | Simple, familiar, safe to service | High current, heavy copper, high distribution loss at high power |
| 48 V rack bus | Four times less current for the same power | Additional conversion stage between the bus and the load |
| Higher-voltage DC distribution | Lower current over longer distances | New protection and isolation practice, more conversion electronics |
Where efficiency losses become money
Every conversion stage loses a fraction of what passes through it, and a data centre converts energy several times between the incoming supply and a processor. Each stage’s loss is paid for twice: as electricity that was purchased and not used, and as heat that the cooling system has to remove, which itself consumes electricity. That double cost is why a small efficiency difference at a large scale becomes a visible operating expense rather than a rounding error. Related design articles for conversion stages are available in the power supply application design hub.
It is also why the useful metric is not the efficiency of a single component but the efficiency of the path. A power supply that is efficient at full load and poor at light load looks good on a specification sheet and behaves differently in a facility where average load is well below capacity. That is the same lesson the 80 PLUS programme encodes for desktop supplies, extended to a much larger scale.
How much semiconductor content rises
More conversion stages mean more switching devices, more rectification and more control, so a rack designed around a higher-voltage DC bus contains more power semiconductors than one using a simple low-voltage bus. Three roles grow in particular. The rectification and power factor stage at the front end, which converts the incoming supply. The intermediate conversion stage, which creates the bus, and which is where wide bandgap devices are attractive because they can switch at a higher frequency with lower loss, allowing smaller magnetics. And the point-of-load stage, where many small converters sit close to the processors.
Protection grows with them. A higher-energy bus needs devices that can absorb more energy during a fault or a transient, and those devices have voltage, current and thermal ratings that have to be selected against the fault energy rather than against the normal operating current.
Cooling as a design constraint
Cooling is not a separate subject from power; it is the same subject seen from the other side. Every watt lost in a conversion stage becomes a watt that the cooling system must move, and the cooling system consumes energy to do it. That means the traditional air-cooled hall runs into a limit determined by how much heat air can carry out of a given volume, which is why direct liquid cooling has moved from a specialist option into mainstream design.
The semiconductor consequence is indirect and real. Liquid cooling removes heat from a smaller surface area than air, which changes the thermal path from junction to coolant, and it changes the ambient temperature a device sees. A part selected for an air-cooled environment with a certain ambient may not be the right selection for a colder coolant and a denser board. This is the kind of decision that should be made from the datasheet rather than from habit.
Supply constraints to expect
Three bottlenecks have historically appeared when computing demand rises quickly. The first is the high-end logic supply, which is outside the scope of this blog. The second is the power chain: switching devices, controllers and the magnetics that go with them, which are less glamorous and have their own capacity. The third is the electrical and cooling infrastructure of the building, which cannot be expanded at the speed of an equipment order.
For a buyer of power devices, the practical implication is that a lead time for a modest transistor can be the constraint on a project with a very large budget. That is why the qualification of a second source is worth doing during the design, not during the shortage.
What is uncertain in these forecasts
Four things are genuinely uncertain. The utilisation of the installed capacity, because a facility built for peak training load behaves very differently when it runs inference at lower power. The pace of efficiency improvement in the computation itself, which changes the energy per unit of work. The shape of the electrical architecture, because a standard that wins could change the device mix substantially. And the constraints outside the industry, principally grid connection and water use for cooling, which are decided by bodies outside the technology sector.
What is more certain is the direction of the engineering: more power in less space, which means higher distribution voltages, more conversion stages and more semiconductor content per rack. That is a statement about architecture rather than about any particular year’s growth.
Summary table
| Change | Component implication | Still open |
|---|---|---|
| More power in the same rack volume | Higher-current paths and more point-of-load conversion | Which bus voltage becomes standard |
| Higher bus voltage | Devices with higher blocking ratings and better switching loss | How much protection moves to the rack |
| Liquid cooling | Different thermal paths and ambient conditions to select for | Standard coolant temperatures |
| Running cost dominated by efficiency | Emphasis on part-load efficiency rather than full-load | How fast computation efficiency improves |
How to use this report without over-fitting
- Separate what is measured (shipments, ASP bands) from what is opinion (CAGR to 2030).
- Map claims to your BOM families: Si Schottky, FRD, MOSFET, IGBT, SiC.
- Prefer dual-source packages over single-source exotic outlines when volumes are uncertain.
FAQ
Are the market size numbers in articles exact?
Treat them as directional unless you have the primary analyst table and identical scope. Definitions of “power semiconductor” differ widely.
What should purchasing do with a bullish forecast?
Negotiate forecast flexibility, not only price. Ask for package-level lead times and PCN policy.
Does AI / EV demand change discrete diode selection?
It raises current density and thermal expectations in adjacent rails (48 V, AUX, sensors). The diode still needs a normal V/I/thermal worksheet.
Where should engineers go next?
Pair this overview with a concrete selection guide such as power MOSFET selection or power rectifier selection.
Continue through this engineering topic
- Power Semiconductor Market Outlook 2026 2030
- Silicon Carbide Market 2026
- Automotive Semiconductor Report 2026
- China Power Semiconductor Industry 2026
- Component Lead Times 2026
- Discrete Diode Market Explained
- Application Design Center
Topic hub: Power semiconductor market outlook 2026–2030 — related selection guides and application notes in this cluster.