Low Capacitance ESD Diode: Protecting High-Speed Signal Integrity in Modern Electronics

A low capacitance ESD diode keeps 3.5 pF off a high-speed line. Why 45 pF parts are wrong there, and how capacitance, clamping and IEC levels decide.

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Low Capacitance ESD Diode: Protecting High-Speed Signal Integrity in Modern Electronics

A low capacitance ESD diode exists because protection and signal integrity pull in opposite directions. On a 50 Ω line, 3.5 pF adds a time constant of about 0.18 ns while a 35 pF part adds about 1.75 ns — and at USB 2.0 speeds a bit is roughly 2 ns long. That factor of ten is why the same clamp that is perfectly adequate on a supply pin is unusable on a data pair, and why the capacitance column, not the ESD level, is the first thing to read.

Last updated: October 16, 2026

Key Takeaways

A low capacitance ESD diode is a transient voltage suppressor engineered so that its parasitic capacitance does not disturb the line it protects.
Read capacitance where it will be measured: at a stated frequency and bias, because the number changes with both, and for differential pairs check the matching between lines as well as the absolute value.
ESD level and capacitance are separate claims. A part can be rated to IEC 61000-4-2 level 4 at 15 kV air and 8 kV contact discharge and still be usable on a high-speed pair.
Leakage is the third number: 150 nA maximum is a different design budget from the microamp-class leakage of a general surge suppressor.
For multi-line interfaces, a matched array removes the per-line tolerance question that separate diodes introduce.

What “Low Capacitance” Actually Costs and Buys

The protection element is a junction; the capacitance is a property of that junction and cannot be wished away, only engineered down.

Two real parts show the two ends of the trade. STMicroelectronics’ USBLC6-2 is an application-specific ESD protection device for high-speed interfaces: 3.5 pF maximum line capacitance, 150 nA maximum leakage, IEC 61000-4-2 level 4 at 15 kV air and 8 kV contact discharge, a capacitance matching tolerance of 0.015 pF from I/O to ground, and stated compatibility with USB 2.0 at up to 480 Mb/s and 10/100 Mb/s Ethernet, in a SOT-666 outline measuring 2.9 mm² maximum. Nexperia’s PESD5V0S1BA is the other end: a bidirectional ESD protection diode rated at 130 W peak pulse power, clamping at 14 V, leaking just 5 nA and surviving more than 30 kV — with 35 pF typical capacitance that makes it a signal-line device for slower nodes and a supply-pin device, not a high-speed pair.

Parameter	ST USBLC6-2	Nexperia PESD5V0S1BA
Role	Application-specific ESD protection for high-speed interfaces	Bidirectional ESD protection diode for one line
Line capacitance	3.5 pF maximum	35 pF typical, 45 pF maximum at 1 MHz, V_R = 0
Leakage	150 nA maximum	5 nA
ESD rating	IEC 61000-4-2 level 4: 15 kV air, 8 kV contact	Greater than 30 kV; IEC 61000-4-2 level 4
Surge rating	Protection of two data lines plus V_BUS	130 W peak pulse power; 12 A IEC 61000-4-5 surge
Clamping / standoff	Per interface requirements	Clamp 14 V at a 5 V standoff
Matching	0.015 pF I/O to ground tolerance	Single-line device
Package	SOT-666 (2.9 mm² max) or SOT23-6L	SOD323, 1.7 mm × 1.25 mm

The Calculation That Decides Which Column Matters

Convert capacitance into time and compare it with the bit period; the answer is usually unambiguous.

3.5 pF on a 50 Ω line: τ ≈ 50 × 3.5 × 10⁻¹² = 0.18 ns.
35 pF on the same line: τ ≈ 1.75 ns.
At USB 2.0 high speed a bit occupies about 2 ns, so the second figure sits inside the bit and the first does not.

This is a first-order model with a stated 50 Ω line impedance — real traces have their own impedance and the eye diagram is the final arbiter — but it explains why interface-specific parts are specified with a maximum capacitance and a matching tolerance rather than with a power class alone. It also explains why the same article cannot recommend one part for both a power rail and a data pair: on the rail the capacitance is irrelevant and the energy handling is everything, and on the pair it is the reverse.

Selecting One Without Trading Away Protection

Start from the interface, then narrow by four numbers. Identify the standard and the signalling rate first, because they set the capacitance ceiling; USB 2.0 at 480 Mb/s and a 10/100 Mb/s Ethernet link do not tolerate the same loading. Confirm the ESD level the product must survive, and check that the part states it as a device-level claim — IEC 61000-4-2 level 4 with the air and contact figures is the usual way it is written. Then check leakage against the system budget, since 5 nA and 150 nA matter differently on a battery-backed node. Finally, resolve the mechanical side: the outline, the pad area and, for multi-line interfaces, whether an array with matched capacitance gives a cleaner layout than several discrete parts.

Two boundary conditions cancel good candidates. The first is capacitance quoted without conditions — a figure taken at a different bias or frequency is not comparable with yours. The second is protection quoted without a device-level standard, because a headline kilovolt number without the test configuration behind it cannot be checked. Where a supplier provides derating, capacitance curves and qualification documents, the selection becomes a matter of arithmetic rather than of trust.

Where These Parts Belong

They sit at the entry point of a high-speed interface, and the placement is part of the specification. USB-C and USB 2.0 ports, HDMI and display links, Ethernet, SIM and video lines, and automotive communication buses are the standard homes; the shared requirement is a connector that a person or a cable can touch. In layout terms that means the diode goes as close to the connector as the routing allows, with a short, low-inductance return path, because a long trace between the connector and the clamp reduces the effectiveness of a device that is already working in nanoseconds.

Verify both the signal path and the ESD discharge path

Place protection with the entry point and current return in mind. On an exposed connector, the discharge should reach the protection device before a long trace carries it toward the sensitive circuit. TI's ESD protection layout guide explains the role of parasitic inductance and return routing. The exact routing must also meet the interface’s signal-integrity constraints.

Compare the signal with the protection populated and with the intended reference configuration, using an eye diagram or the applicable interface measurement. Evaluate system-level ESD using the relevant test setup. TI's system-level ESD design guidance distinguishes IEC testing from component HBM testing; passing one does not prove the other. Low capacitance alone does not determine a protection device’s surge capability.

FAQ

What is a low capacitance ESD diode?

It is a transient voltage suppressor designed with a small junction capacitance so that it can protect a high-speed line without degrading the signal. The capacitance is usually specified as a maximum at a stated frequency and bias.

How low does the capacitance need to be?

Low enough that its time constant on your line impedance is small compared with the bit period. On a 50 Ω line, 3.5 pF gives about 0.18 ns while 35 pF gives about 1.75 ns, which is the difference between a part that suits a 480 Mb/s interface and one that does not.

Why does capacitance matching matter on differential pairs?

Because unequal capacitance on the two lines skews the edge timing between them. Interface-specific parts publish a matching tolerance — 0.015 pF from I/O to ground in the part quoted here — which is difficult to guarantee with two independently toleranced discrete diodes.

Does a lower capacitance part protect less?

Not necessarily, but the two are related and both must be checked. A low-capacitance device is still rated to a device-level ESD standard; what it may give up is the energy handling of a larger surge suppressor, so confirm both the ESD level and any surge rating for the events your connector can see.

What should be confirmed before approving one?

Capacitance at the stated test conditions, the ESD standard and level with its test configuration, leakage at the operating voltage, the matching tolerance for differential lines, the package and pad layout, and the qualification evidence for the target market.

Official Resources

References

STMicroelectronics, USBLC6-2 — very low capacitance ESD protection, DS4260 Rev 7 — source of the 3.5 pF maximum line capacitance, 150 nA maximum leakage, IEC 61000-4-2 level 4 ratings of 15 kV air and 8 kV contact discharge, the 0.015 pF I/O-to-ground matching tolerance, USB 2.0 support to 480 Mb/s, and the SOT-666 and SOT23-6L package areas. st.com — USBLC6-2 datasheet (PDF)
Nexperia, PESD5V0S1BA — Bidirectional ESD protection diode — source of the 35 pF typical and 45 pF maximum capacitance at 1 MHz and 0 V bias, 5 nA leakage, 130 W peak pulse power, 14 V clamping voltage, the greater-than-30 kV ESD rating, the 12 A IEC 61000-4-5 surge current and the SOD323 outline. assets.nexperia.com — PESD5V0S1BA datasheet (PDF)
STMicroelectronics, SM6TxxA, SM6TxxCA — 600 W TVS in SMB — reference for what a surge-class device specifies instead of a line-capacitance figure, including IEC 61000-4-2 and IEC 61000-4-4 coverage. st.com — SM6T series datasheet (PDF)

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