USB ESD Protection Diodes: Selection, Pin Mapping and PCB Layout

Updated: October 28, 2026

USB ESD protection must clamp each pin without ruining the eye diagram: pick V_RWM above the pin’s normal voltage, keep capacitance inside the USB generation’s budget, and place the diode on the connector side of series elements with a short, wide return to the shield/chassis reference.

Data pins, CC/SBU pins on USB-C, and VBUS need separate decisions. A single “USB ESD diode” search result that ignores capacitance or layout will pass a catalog filter and still fail EMC or enumeration. Application notes such as Semtech’s USB 2.0 ESD protection discussion emphasize pin class and parasitic loading—use the same discipline here.

For clamp math beyond USB, see the TVS diode selection guide and what a TVS diode is.

Pin class	Typical concern	Protection focus
USB 2.0 D+/D−	Capacitance vs 480 Mbps	Low-C bidirectional ESD array
USB 3.x SS pairs	Very low capacitance, layout symmetry	Ultra-low-C devices; treat each pair
USB-C CC / SBU	Orientation, PD signaling	Voltage rating for idle/active states
VBUS	Energy, not only ESD	Higher-energy TVS / surge plan

Which USB pins need separate protection decisions?

Separate data, control and power paths.

A USB-C connector does not define one data rate or one supply voltage. Its implemented functions determine the protection requirements.

Pin group	Function	Main protection questions
D+ / D−	USB 2.0 data	Signal loading, clamping and working range
High-speed differential lanes	Supported faster data interfaces	Insertion loss, routing and channel loading
CC1 / CC2	Type-C attachment and configuration	Normal voltage and possible power-pin faults
SBU1 / SBU2	Supported sideband functions	Mode-specific signal and fault requirements
VBUS	Power delivery	Actual negotiated range, surges and overvoltage

TI’s ESD and surge guide for USB interfaces shows why a port needs multiple protection choices. Map only the functions the design actually implements; unused and repurposed pins also need review against the connector and controller requirements.

USB Power Delivery is not universally limited to 20 V or 100 W. USB-IF’s Power Delivery overview describes Extended Power Range up to 48 V and 240 W for supported systems. A particular port, cable and charger may support less. Choose the VBUS protection from the actual product specification.

How do working voltage and clamping voltage differ?

Working voltage describes normal operation; clamping describes stress.

The reverse working voltage must accommodate the line’s specified normal range. The clamping behavior must be evaluated with the protected circuit and transient conditions.

A breakdown voltage is measured at a stated current; it is not necessarily the voltage an IC sees during an ESD event. A quoted clamp value also belongs to a specific pulse or measurement. Compare candidates at relevant current, polarity and waveform rather than selecting the lowest voltage printed anywhere in a table.

Dynamic resistance helps describe how voltage rises with current in the conducting region, but does not remove the effects of early overshoot or board inductance. The resulting voltage at the IC can differ from a device measurement on a reference fixture.

Normal signal swings and tolerances need margin to avoid leakage or unintended loading. At the same time, excessive residual voltage may damage the protected input. The correct choice lies in the complete operating and stress window, not in maximizing one voltage rating.

How much capacitance is acceptable on a data line?

Use the complete interface’s signal-integrity budget.

No single capacitance limit covers every USB implementation. Compare the same capacitance definition and include the connector, package, traces and receiver.

A data sheet may report line-to-ground or line-to-line capacitance at a particular bias and frequency. These are not interchangeable measurements. A favorable typical value also does not describe its tolerance or the entire channel’s frequency response.

TI’s discussion of ESD capacitance and signal integrity illustrates the eye-diagram consequences of excessive loading. Where available, use insertion-loss plots and validated models along with the capacitance number.

As a simple loading illustration, a 1 pF ideal capacitor has a reactance magnitude of about 159 Ω at 1 GHz: |X_C| = 1 / (2πfC). This is not a USB pass/fail calculation; an ESD array and routed differential pair are more complex. It explains why an apparently small capacitance deserves attention at high frequency.

Reading a USB ESD data sheet: a worked example

The same data sheet can quote different capacitances for different connections. In TI’s TPDxEUSB30 data sheet, revision G, section 6.5, the following are typical capacitances measured at 2.5 V bias and 100 kHz.

The 0.05 pF entry must not be substituted for the capacitance from each signal line to ground. Likewise, similar part names do not establish the same working range: section 6.3 specifies 0 to 5.5 V for TPD2EUSB30 and TPD4EUSB30, versus 0 to 3.6 V for TPD2EUSB30A.

These are examples of reading conditions, not a recommendation for every USB port. None of those signal-line ranges establishes suitability for a higher-voltage VBUS connection or a sustained short to VBUS. Confirm the exact device, package, signal range and channel response before comparing alternatives.

How should you route the diode on the PCB?

Give the transient a short, controlled diversion path.

Place protection near the entry point and maintain suitable data routing through the footprint. Review the return path as carefully as the signal path.

A long branch from the connector trace to the diode can leave the sensitive input exposed and create an unwanted stub. A flow-through package can simplify routing when its pin assignment matches the design. Follow the recommended footprint and keep the intended differential geometry through the protected region.

TI’s ESD protection layout guide explains how parasitic paths affect protection. Ground connections, vias and planes must provide a suitable high-frequency return; a connection drawn as ground in the schematic is not an ideal zero-inductance node.

For an illustrative return-path inductance of 2 nH and a current change of 10 A/ns, V = L × di/dt gives 20 V. Those assumed inputs are not a measured USB event or a clamp prediction. They show why shortening and improving a current path can matter as much as changing the diode.

Is ESD protection enough for USB-C power-pin faults?

No; sustained faults require appropriate fault protection.

A short transient clamp is not automatically suitable for continuous exposure to VBUS. Protection for CC or SBU must consider credible shorts to adjacent power pins.

An ESD diode that safely clamps a brief pulse may overheat if a high-voltage rail remains connected. A short-to-VBUS or overvoltage protection circuit may isolate the affected line, limit current or coordinate with other devices. Choose the arrangement for the fault duration and controller limits.

Also distinguish ESD from surge, hot-plug behavior and cable-discharge events. Their waveforms and energy can differ. Passing one specified stress does not prove immunity to all the others.

For VBUS, review the negotiated range, startup and any power-path switch or current limiter. For data and control pins, review whether the protection network remains safe when the local IC supply is off. The schematic must account for the powered and unpowered states.

What does an ESD rating actually prove?

It proves a result only within the stated test scope.

Device-level handling ratings and system-level port immunity are different. Voltage labels cannot be compared without the discharge method and pass criteria.

The stress waveform, contact or air-discharge method, polarity, number of events and tested connection affect the result. A component’s claimed survival rating is not a certification for the assembled device.

TI’s USB protection guide distinguishes the need for system-level protection. Component handling robustness can help during manufacturing but does not remove the need to assess the exposed connector.

Define what a pass means: no damage, no unacceptable reset, normal communication afterward, or another product-specific criterion. Temporary upset and permanent failure are different outcomes and should both be recorded. Apply the target product’s required test plan rather than inventing a universal immunity level from an example design.

How do you validate a protected USB port?

Verify communication and protection on the finished design.

Use the production routing and representative assemblies. The ESD device, connector, enclosure and return paths work together during a stress event.

1. Record supported data modes and normal voltage ranges by pin group.
2. Compare working voltage, clamp measurements, capacitance and package routing.
3. Check signal integrity with the protection installed.
4. Test the required ESD polarities, entry points and operating states.
5. Verify recovery, communication and leakage after testing.
6. Assess separately required surge and sustained-fault conditions.

Keep the exact device code, footprint and document revision in the validation record. A substitute with similar typical capacitance may differ in clamping, package inductance or channel topology. Recheck the consequences before changing the BOM.

For a low-voltage supply powering the port, our SMPS overview explains the power path. A supply’s output protection does not automatically protect its USB data pins.

What capacitance budget should a USB data-line diode meet?

Stay inside the channel’s total capacitance allowance after connector and PCB parasitics.

USB 2.0 high-speed designs commonly target only a few picofarads of added capacitance per line from the suppressor; SuperSpeed budgets are tighter and more sensitive to imbalance. Always read I/O capacitance at the bias voltage your lines actually see—zero-volt catalog figures can mislead.

Interface	Design habit	Failure mode if ignored
USB 2.0 HS	Sum diode C with connector/PCB; check eye	Marginal enumeration or CRC errors
USB 3.x / 3.2	Per-pair ultra-low C; matched stubs	Link training fail, EMI peaks
USB-C CC	Respect PD voltage levels on CC	False attach / contract issues
VBUS	Separate surge energy rating from ESD class	Shorted TVS on hot-plug events

Layout still decides success: place the device within millimeters of the connector pins, keep the ESD return short to the shield reference, and avoid stubbing high-speed traces through long vias to a distant diode. Package options such as SOD-523 arrays appear in SOD-523 ESD protection diodes when board density is the constraint.

Selection checklist before you freeze the MPN

• Confirm working voltage (V_RWM) sits above the rail maximum including tolerance.
• Match surge waveform and peak pulse power (P_PPM) to the threat—not only the catalog wattage label.
• Check clamping voltage at the expected surge current against IC absolute-max ratings.
• For high-speed lines, verify capacitance and whether unidirectional or bidirectional polarity fits the signal.
• Re-check derating curves at your board temperature; catalog P_PPM is usually at 25 °C.

Ratings that decide real protection

Parameter	What to verify	Why it matters
VRWM	Above max continuous voltage	Avoids leakage and false clamping in normal operation
VC @ IPP	Below protected IC abs-max	Clamping too high still destroys the load
PPPM / waveform	8/20 µs vs 10/1000 µs as applicable	Watt labels are not interchangeable across pulses
Cj	Budget for USB/HDMI/RF integrity	Excess capacitance closes eyes on fast edges

FAQ

Unidirectional or bidirectional TVS—how do I choose?

Use unidirectional on DC rails with a defined polarity; use bidirectional on AC or reversible/signal lines where either polarity can appear.

Does a higher wattage TVS always protect better?

No. Clamping voltage, waveform rating, and layout often matter more than the wattage label alone.

Where should the TVS sit on the PCB?

At the entry connector with a short return to the surge ground—long stubs raise inductive overshoot.

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Topic hub: TVS diode selection guide — related selection guides and application notes in this cluster.