USB ESD Protection Diodes: Selection, Pin Mapping and PCB Layout

A USB ESD protection diode diverts a short electrostatic-discharge transient away from vulnerable circuitry while adding as little loading as practical to the normal signal. Selection depends on the protected pin: high-speed data, configuration, sideband and power pins have different voltage and signal-integrity requirements. A diode rating alone does not prove that the finished port survives an ESD test.

Start with a pin map and the port’s supported functions. Then compare electrical data, routing and the complete protection network. This avoids fitting a low-capacitance data-line device onto a power rail where it cannot tolerate normal operation.

Which USB pins need separate protection decisions?

Separate data, control and power paths.

A USB-C connector does not define one data rate or one supply voltage. Its implemented functions determine the protection requirements.

Pin group	Function	Main protection questions
D+ / D−	USB 2.0 data	Signal loading, clamping and working range
High-speed differential lanes	Supported faster data interfaces	Insertion loss, routing and channel loading
CC1 / CC2	Type-C attachment and configuration	Normal voltage and possible power-pin faults
SBU1 / SBU2	Supported sideband functions	Mode-specific signal and fault requirements
VBUS	Power delivery	Actual negotiated range, surges and overvoltage

TI’s ESD and surge guide for USB interfaces shows why a port needs multiple protection choices. Map only the functions the design actually implements; unused and repurposed pins also need review against the connector and controller requirements.

USB Power Delivery is not universally limited to 20 V or 100 W. USB-IF’s Power Delivery overview describes Extended Power Range up to 48 V and 240 W for supported systems. A particular port, cable and charger may support less. Choose the VBUS protection from the actual product specification.

How do working voltage and clamping voltage differ?

Working voltage describes normal operation; clamping describes stress.

The reverse working voltage must accommodate the line’s specified normal range. The clamping behavior must be evaluated with the protected circuit and transient conditions.

A breakdown voltage is measured at a stated current; it is not necessarily the voltage an IC sees during an ESD event. A quoted clamp value also belongs to a specific pulse or measurement. Compare candidates at relevant current, polarity and waveform rather than selecting the lowest voltage printed anywhere in a table.

Dynamic resistance helps describe how voltage rises with current in the conducting region, but does not remove the effects of early overshoot or board inductance. The resulting voltage at the IC can differ from a device measurement on a reference fixture.

Normal signal swings and tolerances need margin to avoid leakage or unintended loading. At the same time, excessive residual voltage may damage the protected input. The correct choice lies in the complete operating and stress window, not in maximizing one voltage rating.

How much capacitance is acceptable on a data line?

Use the complete interface’s signal-integrity budget.

No single capacitance limit covers every USB implementation. Compare the same capacitance definition and include the connector, package, traces and receiver.

A data sheet may report line-to-ground or line-to-line capacitance at a particular bias and frequency. These are not interchangeable measurements. A favorable typical value also does not describe its tolerance or the entire channel’s frequency response.

TI’s discussion of ESD capacitance and signal integrity illustrates the eye-diagram consequences of excessive loading. Where available, use insertion-loss plots and validated models along with the capacitance number.

As a simple loading illustration, a 1 pF ideal capacitor has a reactance magnitude of about 159 Ω at 1 GHz: |X_C| = 1 / (2πfC). This is not a USB pass/fail calculation; an ESD array and routed differential pair are more complex. It explains why a apparently small capacitance deserves attention at high frequency.

How should you route the diode on the PCB?

Give the transient a short, controlled diversion path.

Place protection near the entry point and maintain suitable data routing through the footprint. Review the return path as carefully as the signal path.

A long branch from the connector trace to the diode can leave the sensitive input exposed and create an unwanted stub. A flow-through package can simplify routing when its pin assignment matches the design. Follow the recommended footprint and keep the intended differential geometry through the protected region.

TI’s ESD protection layout guide explains how parasitic paths affect protection. Ground connections, vias and planes must provide a suitable high-frequency return; a connection drawn as ground in the schematic is not an ideal zero-inductance node.

For an illustrative return-path inductance of 2 nH and a current change of 10 A/ns, V = L × di/dt gives 20 V. Those assumed inputs are not a measured USB event or a clamp prediction. They show why shortening and improving a current path can matter as much as changing the diode.

Is ESD protection enough for USB-C power-pin faults?

No; sustained faults require appropriate fault protection.

A short transient clamp is not automatically suitable for continuous exposure to VBUS. Protection for CC or SBU must consider credible shorts to adjacent power pins.

An ESD diode that safely clamps a brief pulse may overheat if a high-voltage rail remains connected. A short-to-VBUS or overvoltage protection circuit may isolate the affected line, limit current or coordinate with other devices. Choose the arrangement for the fault duration and controller limits.

Also distinguish ESD from surge, hot-plug behavior and cable-discharge events. Their waveforms and energy can differ. Passing one specified stress does not prove immunity to all the others.

For VBUS, review the negotiated range, startup and any power-path switch or current limiter. For data and control pins, review whether the protection network remains safe when the local IC supply is off. The schematic must account for the powered and unpowered states.

What does an ESD rating actually prove?

It proves a result only within the stated test scope.

Device-level handling ratings and system-level port immunity are different. Voltage labels cannot be compared without the discharge method and pass criteria.

The stress waveform, contact or air-discharge method, polarity, number of events and tested connection affect the result. A component’s claimed survival rating is not a certification for the assembled device.

TI’s USB protection guide distinguishes the need for system-level protection. Component handling robustness can help during manufacturing but does not remove the need to assess the exposed connector.

Define what a pass means: no damage, no unacceptable reset, normal communication afterward, or another product-specific criterion. Temporary upset and permanent failure are different outcomes and should both be recorded. Apply the target product’s required test plan rather than inventing a universal immunity level from an example design.

How do you validate a protected USB port?

Verify communication and protection on the finished design.

Use the production routing and representative assemblies. The ESD device, connector, enclosure and return paths work together during a stress event.

Last updated: October 11, 2026

1. Record supported data modes and normal voltage ranges by pin group.
2. Compare working voltage, clamp measurements, capacitance and package routing.
3. Check signal integrity with the protection installed.
4. Test the required ESD polarities, entry points and operating states.
5. Verify recovery, communication and leakage after testing.
6. Assess separately required surge and sustained-fault conditions.

Keep the exact device code, footprint and document revision in the validation record. A substitute with similar typical capacitance may differ in clamping, package inductance or channel topology. Recheck the consequences before changing the BOM.

For a low-voltage supply powering the port, our SMPS overview explains the power path. A supply’s output protection does not automatically protect its USB data pins.

FAQ

Can an ordinary rectifier diode protect a high-speed USB line?

Do not assume so. Its capacitance, clamp behavior and current path may be unsuitable. Select and validate a device intended for the signal and transient conditions rather than reusing a power rectifier by shape.

Does a USB-C connector guarantee a high data rate?

No. Connector form, supported data protocol and power-delivery capability are separate properties. Use the product’s implemented interface specification when selecting protection.

Is an unpowered USB controller protected by the same diode?

That depends on the protection network. Review possible current into supply rails, back-powering and clamp paths when the local supply is off. Test the required unpowered state explicitly.

Can a higher ESD voltage rating replace layout validation?

No. Parasitic paths can raise the residual voltage at the IC even when the diode survives. Check the finished layout and system behavior alongside the component’s rating.

What belongs in the final protection record?

Keep the pin map, normal and fault voltage ranges, chosen device, routing constraints and test results together. The useful outcome is a protected interface that communicates correctly and meets its defined stress criteria, not simply the lowest capacitance or largest ESD number in a catalogue.

Continue through this engineering topic

For the complete selection, design, verification, and troubleshooting path, explore the TVS ESD and Surge Protection Hub.

• Practical guide: What Is a Low Clamping Voltage TVS?
• Practical guide: What makes an SMBJ TVS diode the right choice for surge protection?
• Practical guide: Is an SMAJ TVS Diode the Right Surge Protector for Your Design?
• Ask Good-Ark technical support about this application