ESD Protection on Boards: Why the Small IC-Side Diode Matters as Much as the Big TVS

A board can carry a large TVS at its power entry and still fail ESD tests, because the two threats are different jobs. The TVS guards the line-to-ground energy of a surge — the big pulse that comes in through the mains or a connector — while electrostatic discharge strikes at a different scale and a different place: the IC pin, the signal line, and the transceiver, where a tiny energy event at the wrong moment corrupts a signal or latches a logic state. The small IC-side ESD diode is the device that lives at that second point, and on a board with high-speed interfaces it matters as much as the big TVS, because it protects exactly the parts the TVS never reaches. This article draws the division of roles, compresses the ESD event physics, and maps where the small diode goes.

Why the Small IC-Side Diode Matters as Much as the Big TVS

The division of labor on a protected board is clean once it is stated: the TVS protects the power entry against line-to-earth energy, and the ESD diode protects the IC-side signal pins against human-touch and air-discharge events. The TVS is sized for joules — the energy of a lightning-coupled surge. The ESD diode is sized for the very different threat of a charged body approaching a connector or a data pin, where the discharge is short, high-voltage, and high-frequency, and its damage is to the signal integrity and the silicon gate rather than to the rail.

The consequence is that a board with only a TVS is not ESD-protected, and a board with only IC-side diodes is not surge-protected — each device guards its own zone. The transient voltage suppressor covers the power-entry role, and the ESD family articles cover the signal-side role; this article is the positioning that tells a designer which is which on the same board.

The practical framing for a board designer: the TVS answers “what happens if the line takes a hit?”, and the ESD diode answers “what happens if someone touches the connector?” Both questions matter, and one device cannot answer both.

Air Discharge Events and the HBM Model in One Picture

The ESD event the IC-side diode guards is modeled by the HBM (human body model) standard: a charged human body at a few kilovolts discharges into a device through a defined capacitance and resistance, producing a fast, high-voltage pulse at the point of contact. The model defines the test the ESD part must survive — the IEC 61000-4-5 and HBM test waveforms are the reference for what “ESD protection” is measured against.

The physics in one picture: the body stores charge at high voltage but low energy, and when it touches a connector or data pin, that charge dumps through the point of contact in microseconds. The voltage is kilovolts, which would destroy an unprotected IC pin; the energy is small because the body-model capacitance is small. The small ESD diode sits at that point and shunts the discharge to ground before it reaches the silicon.

The surge and ESD test article covers the HBM and IEC waveforms in detail; the relevant point here is that the model defines both the threat and the test the ESD diode must pass.

Placing the Diode: IC Pin, Connector, or Both

The placement of the ESD diode is decided by the entry path of the discharge. A discharge can enter at the IC pin through a signal line that carries it, at the connector itself, or at both if the board is exposed at multiple points. The placement tiers are: at the pin for direct protection of the silicon, at the connector for first-line defense where the discharge enters, and both for the fully protected path.

The IC-pin placement protects the silicon directly and is the minimum for a logic device; the connector placement protects the entry point and is the minimum for a port that users touch. A USB or CAN port on a product that humans touch usually earns both, because the connector blocks the entry and the pin diode protects the silicon from whatever leaks through the line. The SOD-523 ESD diode profile shows the small-package part that fits the pin-side role.

The automotive ESD suppressor and multi-line ESD array articles show how the placement tier scales when many signal lines need the same pin-side defense.

The role division is easiest to hold as a table:

Device	Protects	Threat scale	Sits at	Key constraint
TVS	Power entry, rail	Surge joules	Line to ground	Clamping voltage, energy
ESD diode (IC-side)	Signal pins, silicon	HBM kilovolts, low energy	Data line to ground	Capacitance budget, speed
ESD diode (connector)	Port entry	Air discharge	Connector pin	Placement, first-line
Low-C ESD diode	High-speed data	HBM + signal quality	Signal line	Minimal pF

The table makes the two-device board legible: the TVS handles the big energy at the power entry, the ESD diode handles the fast low-energy strike at the pin and connector, and the low-capacitance variant is the compromise for high-speed lines where signal quality is the binding constraint. A designer who can fill this table for a board has answered the “which device where” question that this article starts with.

The HBM model also has a practical counterpoint worth naming: the charged-device model (CDM), where the device itself, not a human, carries the charge. A board or IC that accumulates charge and then touches a grounded point produces a discharge that stresses the pin from inside rather than from a connector. The CDM threat argues for pin-side protection close to the silicon even on boards with no user-touched connector, because the charge can originate on the board itself. The surge and ESD test article covers both models; the takeaway here is that the pin-side diode earns its place in both the human-touch and the self-discharge cases.

Data-Line ESD: Capacitance Budget and Signal Integrity

The data-line ESD diode has a second constraint that the power-side TVS never faces: whatever protection is added to a signal line adds capacitance to that line, and capacitance is budget that high-speed signals cannot afford. Every pF the ESD diode contributes to the line counteracts the signal edge — on a fast digital line, the added capacitance rounds the corners of the eye diagram and closes the receiver’s timing margin.

The result is that the IC-side ESD diode is a compromise device: it must carry the discharge to ground, and it must do so with the smallest possible capacitance contribution. The low-capacitance ESD diode family exists precisely for this job, trading a little protection robustness for the smallest signal impact. The low-capacitance ESD diode article develops the eye-diagram argument in full; the positioning here is that the capacitance budget is a first-order constraint of the same rank as the discharge protection itself.

The selection rule for a data line is therefore two-sided: the diode must survive the HBM discharge, and it must stay within the line’s capacitance budget. A part that passes the first test but blows the second is a failed selection on a high-speed line.

A concrete board decision closes the case. A small product has a USB connector and a microcontroller with an internal USB PHY, on a board with a TVS at the power entry. The USB data lines are high-speed, so the pin-side protection is a low-capacitance ESD diode per line, placed as close to the connector as the layout allows — that placement catches the discharge at the entry before it travels the trace, and the low capacitance keeps the eye open. The VBUS rail, a 5 V power line, gets the same ESD diode to ground because a charged cable can strike it too, but it does not need the TVS at the entry since the power-entry TVS already guards the input. The result is a two-tier board: the TVS for the line, the small low-C diodes for the data and VBUS, each in its own zone — which is exactly the division this article has been drawing.

USB and CAN as Recurring Case Studies

Two familiar buses make the ESD role concrete. A USB port is a recurring ESD entry because users plug and unplug devices constantly, bringing charged bodies near the connector; the USB ESD protection case shows the diode placed on the port’s signal lines and the 5 V rail guarding logic against the discharge. The USB ESD protection article covers the port-level design in depth.

A CAN bus is the automotive mirror: a differential, balanced pair that carries control traffic between nodes in a vehicle, where ESD from wiring looms and the capacitance budget is set by the bus speed. The CAN bus ESD protection article shows the differential-pair placement and the low-capacitance choice the bus demands.

Both cases land on the same conclusion that this article starts with: the small IC-side diode guards a different zone than the TVS, it must respect the capacitance budget, and its placement follows the entry path. The ESD diode categories list the small-package parts for both buses, and the TVS family covers the power-entry role the same board still needs.