In a PDFN leadless package, the exposed bottom pad is the electrical and thermal exit: it carries current, conducts heat into the board, and decides whether the part performs to its datasheet. This guide covers pad design, thermal vias, stencil and reflow, and the inspection that verifies the joint—using the PDFN56 packages of the AMBRP family as the reference.
Leadless Package Construction: The Bottom Pad Story
A PDFN package has no through-hole leads; the electrical connections are flat pads on the bottom, and a large exposed pad in the center is the thermal connection to the PCB. The exposed pad is the design’s center of gravity: current flows through the side pads, heat flows through the center pad, and both depend on the copper the board provides underneath.
The consequence for the layout engineer: a PDFN part is only as good as its footprint. A correct footprint makes the package behave like the datasheet’s RθJC suggests; a starved or voided one silently raises the junction temperature no matter how good the die is.
The same construction principle applies across the leadless family, from small signal packages to the PDFN56 power class; the pad is always the thermal statement.
The side pads carry the electrical current and the center pad carries the heat, but the two share the same solder joint quality: a void that raises thermal resistance can also weaken the mechanical connection that the electrical pads depend on. The inspection treats the whole footprint as one joint.
Pad Design Rules for PDFN56
The PDFN56 package—5 × 6 mm—appears on parts such as the AMBRP10H100 and AMBRP5100. The pad design starts from the package drawing and follows three rules:
- Match the exposed pad. The copper pad under the package should match the exposed pad size from the datasheet outline; undersizing leaves part of the pad unconnected, oversizing invites solder bridging to the side pads.
- Extend the side pads. The side pads should extend slightly beyond the package body for a solder fillet that can be inspected, following the land-pattern recommendation in the package drawing.
- Leave the gap clear. Keep solder mask and copper clear of the space between the center pad and the side pads to prevent bridging.
The values in the package drawing are the starting point; the stencil and reflow settings below are the variables that make the footprint work.
The land pattern choice between copper-defined and solder-mask-defined pads changes the solder volume and the fillet shape; the package drawing’s recommendation is the starting point, and the assembly house’s capability decides the final aperture. Confirm both before the board is released.
Thermal Via Placement Under the Exposed Pad
| Via parameter | Typical guidance (starting point) |
|---|---|
| Via diameter | 0.3 mm class |
| Pitch | 1.0–1.2 mm grid across the pad |
| Layer connection | Connect to inner ground or power planes |
| Solder mask | Mask or tent the vias so solder does not wick away |
The vias do two jobs: they conduct heat from the pad into inner planes, and they reduce the thermal resistance that the RθJA figure assumes. A pad with copper but no vias leaves the heat in the surface layer; a via array spreads it through the board thickness. The guidance above is a recommended starting grid, confirmed against the board stack and the thermal budget.
Via-in-pad design adds another choice: plated vias under the pad can wick solder away during reflow, which is why the guidance includes tenting or masking the vias. Filled or capped vias cost more but keep the solder where the joint needs it; the decision follows the production volume and the thermal requirement.
The via grid also affects the solder joint: vias too close to the pad edge can wick solder from the fillet, so the pattern keeps the outer vias inside the pad area with clearance to the side pads.
Stencil and Reflow Considerations
The stencil opening controls how much solder lands on the pad, and a leadless package balances two risks. Too much solder under a large exposed pad lifts the package or bridges to the side pads; too little leaves voids that add thermal resistance. The common practice is to reduce the stencil opening over the center pad—a pattern of small apertures instead of one solid opening—so the solder volume is controlled and gas can escape during reflow.
The reflow profile follows the lead-free soldering rules in the assembly guide: a ramp that suits the board and package, a peak temperature inside the J-STD-020 limit, and a cooling rate that avoids solder cracks. The package’s moisture sensitivity (MSL) determines whether any baking is needed before reflow.
The aperture pattern under a large pad is a balance: too little solder leaves voids from trapped gas, too much lifts the package or bridges. A common starting pattern uses 60–80% of the pad area in small apertures, confirmed by the X-ray results on the first build.
Inspection: X-Ray and Solder Coverage Checks
Leadless joints hide under the package, so visual inspection is not enough. Two checks catch the failures that matter:
- X-ray inspection of first builds and periodic lots reveals solder voids under the exposed pad and bridging between pads that visual inspection cannot see.
- Thermal verification on the assembled board—measuring case or pad temperature at load—confirms the joint is actually doing the thermal job the footprint promised.
A small void is normal; a large void or a cluster under the die changes the thermal picture. The acceptance criteria follow the assembly standard, and the temperature measurement is the final judge of whether the design intent survived the process.
The acceptance criteria separate the normal from the failure: small, scattered voids are within many assembly specifications, while a large void under the die area or voids above a percentage of the pad change the thermal picture. The percentage thresholds come from the assembly standard and the thermal budget, and the temperature measurement is the tie-breaker.
A well-built PDFN joint is flat and void-controlled; the X-ray image should look consistent across a board, and variation between units is the first sign of process drift.
A worked example fixes the scale: for the 5 × 6 mm PDFN56, the exposed pad sits roughly in the center, the side pads extend beyond the body for the fillet, and a 1.0–1.2 mm via grid under the pad connects to the inner plane on the net defined by the pinout. The exposed pad of a power diode may carry anode or cathode potential, so it is connected according to the datasheet pin definition rather than assumed to be ground. The result is a footprint that lets a 10 A part carry its rated current with the datasheet’s thermal assumption.
The process verification extends beyond the first build: a periodic X-ray sample and a temperature check on production lots catch process drift before it becomes a field failure. The checklist belongs in the assembly spec, not just in the design review.
Standards note. The pad and via guidance above is engineering practice for PDFN56 land patterns, consistent with IPC land-pattern and assembly standards and the package drawing on the AMBRP10H100 and AMBRP5100 datasheets from Good-Ark. Via diameter, pitch, and stencil apertures are recommended starting values to be confirmed against the board stack and the assembly house’s process data; the reflow peak must respect the J-STD-020 moisture and reflow limit.
Frequently Asked Questions
Why does the exposed pad matter so much?
It is the thermal exit: heat flows from the die through the pad into the PCB copper. If the pad is undersized, voided, or starved of vias, the junction runs hotter than the datasheet suggests.
How many thermal vias do I need under a PDFN56 pad?
The grid matters more than the count. A 1.0–1.2 mm pitch array across the pad is a common starting point, connected to inner planes; confirm against the thermal budget and board stack.
Should the stencil open fully over the center pad?
Usually not. A pattern of smaller apertures over the center pad controls solder volume and lets gas escape, reducing voids and preventing the package from floating on excess solder.
How do I inspect a leadless solder joint?
With X-ray for voids and bridging, plus a thermal measurement at load to confirm the joint’s thermal performance. Visual inspection alone cannot see under the package.
What happens if the pad design is wrong?
The part runs hot, current capability shrinks, and the failure shows up in thermal cycling rather than at test. The fix is a footprint revision, not a different brand of the same package.
Conclusion
PDFN design is one rule with three consequences: build the exposed pad properly—size it from the drawing, put a via grid under it, control the solder with stencil apertures, and verify with X-ray and temperature—and the package performs like the datasheet. The design lives under the part, where the datasheet cannot see it.
Start from the AMBRP10H100 product page and its package drawing, compare the AMBRP5100 for the same footprint class, and contact Good-Ark with your board stack and thermal budget for a pad-design review.