Every ESD diode on a signal line adds capacitance to that line, and on a high-speed interface the added capacitance is not a footnote — it is a budget that directly closes the receiver’s eye. A data line protected by a general-purpose ESD diode can lose signal integrity even though the protection works perfectly, because the diode’s own pF slow the edge and blur the timing window. The low-capacitance ESD diode exists for exactly this reason: it carries the discharge to ground with the smallest possible contribution to the line. This article explains the capacitance budget, where the diode adds it, what the low-C part trades away, and how to verify the result on the bench.
One Extra pF and the Eye Starts to Close
The eye diagram is the receiver’s view of the signal: an overlay of every received bit, where the opening of the eye shows the timing and amplitude margin the link has. Every element that adds capacitance to the line rounds the signal edges, and a rounded edge closes the eye — the receiver’s sampling point loses margin, and the bit error rate rises even while the signal still “looks” acceptable on a single capture.
The arithmetic is direct: a small-signal protection diode mounted on a data line contributes its junction capacitance plus the pin and pad capacitance, and on a fast line where the edge width is comparable to the added capacitance’s time constant, the effect is first-order. One added pF can be the difference between a clean eye and a marginal one at a high data rate. The low-capacitance ESD diode article frames the same trade from the part side; this article works the board-side budget that decides whether the part fits.
Where the Diode Adds Capacitance: Pin, Package, and Sitting
The added capacitance is not just the diode’s nominal junction value — it has three sources. The first is the junction itself, the intrinsic capacitance of the device. The second is the package: a larger package with a thicker body and more pad area adds stray capacitance to the mount. The third is the sitting, the placement and pad arrangement on the board, where nearby traces and the grounding path contribute parasitic capacitance on top of the device.
Reading the three sources explains why two “low-capacitance” parts can behave differently in a design: the nominal rating is only the junction term, and the package plus the layout fill in the rest. A part with a modest junction value but a large package can add as much total capacitance as a nominally larger-junction part in a small one. The selection must therefore read the installed contribution, not the headline rating.
The SOD-523 ESD diode profile is the small-package example whose total added capacitance stays low partly because of its footprint, and the CAN bus ESD case is where the same low-C reasoning governs a differential bus.
The Low-C ESD Diode: What You Trade for the Smallest Footprint
The low-capacitance ESD diode wins the signal-integrity budget, and it pays for that win in other properties worth naming. The trade table below is the honest view:
| Property | General ESD diode | Low-C ESD diode |
|---|---|---|
| Junction capacitance | Higher | Lowest in family |
| Discharge energy per event | Higher | Lower — careful on large strikes |
| Signal edge impact | Larger | Minimal |
| Package size | Can be larger | Smallest |
| Best role | Pin protection where C is not critical | High-speed lines, signal-quality critical |
The trade is real: a lower-capacitance junction is typically a smaller or differently built junction, and small junctions absorb less energy per event. On a data line the events are human-touch and air-discharge scale, which small junctions handle; the low-C part would be the wrong choice for a series position carrying a larger strike. The selection is therefore a match of event scale to junction scale, with the capacitance budget as the decider when the line speed matters.
Placement That Saves the Signal: Close to the Pin, Short to Ground
Placement is half the capacitance budget, and the rule is simple: put the diode as close to the protected pin as the layout allows, with the shortest direct path to ground. The close-to-the-pin placement keeps the protected trace short — the discharge is shunted at the entry rather than traveling a long trace that adds parasitic capacitance and gives the strike more path to the silicon. The short-to-ground path minimizes the return-loop inductance and the stray capacitance of a wandering ground trace.
The practical layout form is a ground pad adjacent to the connector or pin, with the ESD diode bridging directly from the line to that pad. The USB ESD protection article shows the connector-side version of the same placement, and the multi-line ESD array shows how the close-and-short rule scales when several lines need the same treatment on one connector.
Quantify the eye-closing effect to make the budget concrete. A high-speed line carries an edge whose rise time is set by the bandwidth: a 10 MHz signal has edge content up to tens of megahertz, and a capacitor on the line with a value C forms a time constant with the line impedance that rounds the edge. A 2 pF diode on a 50 Ω line adds a time constant of about 100 ps; on a signal with a 1 ns edge, that rounding is a tenth of the edge — visible in the eye and a real reduction in the receiver’s timing margin. Doubling the data rate halves the edge and doubles the relative impact of the same 2 pF, which is why low-capacitance parts matter precisely where the interfaces are fastest.
The rule that falls out of the arithmetic is a budget equation: the total added capacitance from the protection (junction plus package plus sitting) must stay small against the line’s time-constant budget, and the budget tightens as the data rate rises. A designer who reads only the junction pF and ignores the package and layout terms can undershoot the budget by a factor of two; the three-source reading from the earlier section is what keeps the accounting honest.
The selection decision between a general and a low-C part follows three questions. First, what is the data rate and edge time — does the interface have any margin to spare? Second, how much total capacitance will the installed protection add, including package and layout? Third, what is the strike scale the part must survive? A slow interface with a comfortable eye can take a general ESD diode; a fast interface or a marginal eye demands the low-C part; and a large-strike position may force a compromise where the capacitance budget and the energy requirement are balanced against each other.
A worked example closes the decision. A 100 Mbps LVDS-style link with a tight eye has about 2 pF of capacitance budget for protection. The candidate low-C diode adds 0.5 pF junction plus a small package and a short layout path, totaling about 1 pF installed — inside the budget, and the eye measurement confirms it. A general-purpose ESD diode in the same position adds 3 pF installed, blowing the budget; the eye closes, and the bit error rate rises even though the protection is perfect. Same protection goal, same board, and the low-C part is the only one that fits — the capacitance budget decided before any ESD test. The same trade repeats on every high-speed interface, which is why the low-capacitance family, not the general part, is the default on data lines that carry real bandwidth. On the board, that means choosing the low-C diode first and confirming the eye second, so the protection never becomes the very thing that degrades the signal it was installed to save.
Verifying on the Bench: Based on Capacitance and Signal Checks
The last step is measurement, and it runs in two parts. First, confirm the protection works: an ESD or HBM-type test must show the discharge shunted at the diode, with the protected pin staying below the damage level. Second, confirm the signal survives: a fast-edge or eye-diagram measurement across the protected line must show the margins holding — the added capacitance must not have closed the eye.
The verification discipline is to measure the signal with the protection in place and compare to the unprotected baseline, because the diode is mounted and its capacitance is in the path whether or not a strike ever occurs. A board whose eye closes when the ESD diodes are added has failed the signal half of the selection even though the protection half passed. The surge and ESD test article covers the HBM test side, and the ESD protection families list the low-C parts whose installed contribution fits the budget once both measurements pass. The overall method this article builds is a two-sided pass/fail: the protection must survive the discharge, and the signal must survive the protection. A low-capacitance ESD diode is the component that satisfies both, but only when its total installed capacitance is counted, its placement is tight, and its event scale is matched — the three habits that turn a good part into a working board.