GaN in AI Data Center Power: Rack PSU Trends and the Discrete Parts Around Them

GaN shows up first in high-frequency conversion stages inside AI rack power shelves and intermediate bus converters, not as a wholesale replacement for every silicon or SiC device from grid to GPU. When people search GaN power for AI data centers, the useful answer is role-based: where the material sits in the chain, what efficiency and density claims require on a datasheet, and which discrete rectifiers, MOSFETs, and TVS parts still surround those stages.

This article deliberately complements—not duplicates—the broader demand overview in AI data centers power semiconductor demand. For chemistry jobs at board level, see also GaN vs SiC vs silicon in power supplies.

Direct answer: where GaN shows up in AI power trains today

GaN is strongest in high-frequency DC-DC and intermediate bus stages that need density.

SiC and silicon still dominate many front-end AC-DC, high-voltage, and rugged clamp roles; hybrid BOMs are normal.

In plain language, AI racks pull large continuous power. Architectures are shifting toward higher DC voltages inside the facility (including industry discussion of 800 V DC class delivery) so that copper losses fall when current falls for the same watts. GaN devices switch fast with low charge, which helps shrink magnetics in intermediate conversions such as 800 V-to-50 V or 800 V-to-12 V class IBCs when the topology and gate drive are designed for that speed. That is a stage win, not a claim that GaN owns the utility transformer or every surge clamp on the shelf.

News hook: Infineon × NVIDIA GaN collaboration

Trade and vendor materials in October 2026 described an expanded Infineon–NVIDIA effort on GaN-based high-voltage intermediate bus converters for AI data center power, building on an earlier 800 V DC collaboration that also involved SiC.

Coverage timed around NVIDIA’s GTC activity in Berlin reported joint work on GaN IBC solutions aimed at high-power AI racks and hot-swappable maintenance concepts, with deployment language pointing toward gradual rollout in the 2027 timeframe for very high rack powers. Treat those dates as vendor roadmap statements. Cross-check with Infineon’s own AI power positioning pages and independent technical articles rather than a single secondary headline. Useful starting points: TrendForce summary of the Infineon–NVIDIA GaN expansion; Infineon “We Power AI” architecture overview; engineering context in EE Power on SiC and GaN supplies for AI.

Rack and PSU architecture in plain language (grid → PSU → board)

Power reaches a GPU through several conversion hops, each with loss and protection needs.

Understanding the hop list prevents treating “GaN for AI” as one magic part number.

A simplified learning path: facility AC (or higher-voltage DC feed) → rack or power-shelf PSU / rectifier stages → intermediate bus voltages → point-of-load or accelerator module regulators → processor rails. Open Compute style shelves often group multiple PSUs; each PSU may take a phase and output a shared DC bus. As rack targets climb from tens of kilowatts toward hundreds of kilowatts and industry discussions of megawatt-class AI factories, distribution losses force higher bus voltages and fewer conversion stages where possible. GaN is one tool inside that redesign. Students can sketch the block diagram before reading any GaN datasheet; the diagram explains why discrete surge and rectifier parts never disappear.

GaN vs SiC vs silicon roles in AI PSUs (job split, not hype)

Each chemistry wins different voltage, frequency, and ruggedness jobs.

GaN favors fast, efficient mid-conversions; SiC favors very high voltage and harsh thermal; silicon remains cost-effective and proven for many stages.

SiC MOSFETs and diodes are common in high-voltage PFC and primary stages where blocking voltage and thermal headroom dominate. GaN HEMTs and related devices shine when switching frequency and size matter at intermediate voltages. Silicon MOSFETs, diodes, and controllers still populate hold-up paths, OR-ing, hot-swap, house-keeping supplies, and many clamps. Hybrid portfolios are what serious vendors describe when they say “grid to core.” If a marketing slide shows only one material, ask which stage it actually switches.

Power density and efficiency claims—what to verify on a datasheet

Density and efficiency claims are test-condition statements, not universal guarantees.

Verify voltage class, R_DS(on) or R_DS(on),max, gate charge, reverse recovery behavior, package thermal resistance, and the exact efficiency test circuit.

Checklist for beginners: compare devices at the same V_DS class and similar current; read whether efficiency includes the gate driver; check SOA and short-circuit notes for rack fault cases; confirm humidity and altitude deratings for data hall environments. Fast edges raise EMI—layout and filter volume can erase a paper density win. For rectifier selection method (even when the main switch is GaN), reuse the discipline in how to select rectifier diodes for SMPS.

Discrete support parts: rectifiers, TVS, and MOSFETs around wide-bandgap stages

Wide-bandgap stages still need silicon companions for surge, OR-ing, and aux rails.

Bill-of-materials risk often hides in those “boring” discretes when GaN gets all the attention.

Expect input-side protection and bridge elements, PFC diodes or sync FETs, bus capacitors with appropriate ripple ratings, output sync rectifiers, and TVS or crowbar strategies for hot-plug and cable events. A clear TVS primer is what is a TVS diode. Good-Ark’s public discrete catalog at en.goodark.com/product.php covers diode and related families used beside high-frequency stages; always match ratings to the rack transient environment rather than copying a consumer charger BOM.

Thermal, EMI, and gate-drive caveats for beginners

Faster switching shifts heat and noise problems; it does not delete them.

Gate-drive layout, kelvin connections, and common-mode paths become first-order design items.

GaN gate voltage windows can be narrower than older silicon MOSFET habits. Overshoot on the gate destroys parts quickly. High dv/dt couples into nearby sense lines and can false-trigger protection. Thermal maps must include copper planes and airflow in dense shelves, not only the FET junction-to-case number. If you are learning, build a low-power GaN eval board before judging rack-scale claims.

Buyer checklist table for AI/server-adjacent power designs

Use the table as a review agenda with vendors and distributors.

Check	Why it matters	Evidence to request
Stage assignment (AC-DC / IBC / PoL)	Wrong chemistry for the stage wastes cost	Block diagram with device families labeled
Voltage and transient envelope	Hot-swap and fault peaks exceed nominal bus	SOA, surge, and clamp coordination notes
Efficiency at realistic load points	Peak number may ignore light-load rack behavior	Efficiency curves at 10/50/100% with setup listed
EMI filter volume	Can erase density gains	Pre-compliance plots or reference design gerbers
Discrete second sources	GaN lead times should not strand silicon clamps	AVL/ALT list for diodes, TVS, sync FETs

How this differs from consumer GaN chargers

Phone chargers proved GaN density; AI racks demand continuous high power, redundancy, and serviceability.

Copying a 65 W adapter playbook into a power shelf is a category error.

Consumer adapters optimize for size, cost, and intermittent loads. AI shelves optimize for uptime, hot-swap, telemetry, and thermal budgets shared across many PSUs. Voltage classes and fault energies are different. Learning from chargers is fine for soft-switching intuition; qualification and protection philosophy must come from server/data-center references.

Good-Ark angle: learning path to diodes/TVS used beside GaN stages

Good-Ark is a discrete semiconductor maker (rectifiers, bridges, and related products) whose public materials help learners study the silicon neighbors of GaN stages.

Use the blog for concepts and the main site for catalogs and documents—without treating either as a rack reference design.

Pair this article with the rectifier and TVS guides linked above, then verify any production part against its datasheet and authorized channel. Certificates and quality pages on en.goodark.com/zzzs.php describe factory systems; they do not automatically certify a specific AI PSU BOM.

800 V DC class architectures and why frequency matters

Higher rack bus voltages reduce current for the same power, which cuts I²R loss in copper.

GaN becomes attractive when the converter that steps that bus down must switch fast to keep magnetics small.

Industry discussions of 800 V DC delivery for AI factories are about distribution physics first. The semiconductor choice comes second: which device can efficiently chop that voltage at the frequency your magnetic design needs, with gate-drive and reliability margins the rack can live with. SiC may still win parts of the front end; GaN may win the intermediate bus. Silicon may still OR, hot-swap, and clamp. When a press release mentions GaN for 800 V-to-50 V or 800 V-to-12 V IBCs, translate it into a schematic block before celebrating a material victory. Also separate facility-level DC from board-level 12 V/48 V habits you already know from enterprise servers—labels sound similar, energy levels do not.

Practical learning path for students and junior engineers

You can learn AI rack power without a megawatt lab.

Start from block diagrams, then datasheets, then low-power GaN eval hardware.

Suggested sequence: (1) sketch grid-to-GPU hops and mark where surge energy lives; (2) read one SiC PFC app note and one GaN half-bridge app note side by side; (3) measure efficiency on a vendor eval board at multiple loads; (4) add a TVS and watch how layout changes residual overshoot; (5) only then read AI-factory marketing PDFs. That order keeps hype downstream of skills. Blog explainers on rectifiers and TVS linked earlier are enough to start the discrete half of the problem.

FAQ

Where is GaN used in an AI data center power chain?

Most often in high-frequency intermediate conversions and dense DC-DC stages inside rack PSUs or IBCs, especially as architectures explore higher DC bus voltages. Front-end AC-DC, very high-voltage, and many protection roles may still use SiC or silicon. Always map the chemistry to the stage on a block diagram rather than assuming one material everywhere.

Is GaN replacing SiC in server PSUs?

Not as a blanket replacement. SiC remains strong at high voltage and harsh thermal corners; GaN competes where switching speed and magnetic size dominate. Vendor roadmaps increasingly describe hybrid Si/SiC/GaN chains from grid to core. Ask which stage a quoted device actually switches.

Which discrete parts still matter next to GaN stages?

Rectifiers or sync MOSFETs, OR-ing and hot-swap FETs, aux supply diodes, and TVS/ESD clamps remain critical. They handle surge, reverse connection, and housekeeping loads that GaN stages are not meant to absorb alone. Select them for the rack transient environment, not from a consumer charger BOM.

Key takeaways

GaN power for AI data centers is a stage-specific story about dense, high-frequency conversion—highlighted by collaborations such as Infineon’s GaN IBC work with NVIDIA—while SiC and silicon keep major roles. Verify datasheet conditions, plan discrete support parts, and keep consumer charger intuition separate from rack power engineering.