The AC loop and the DC loop of a rectifier stage are two antennas, and their size is entirely under the designer’s control. A layout that keeps the loops small stays quiet; one that lets them grow radiates switching noise the components never intended. This article frames the loop-as-antenna idea, shows the trace, via, and component tricks that shrink both loops, covers the thermal pad and via patterns for SMD rectifiers, separates the power ground from the signal ground, and closes with a layout review checklist for a small power board.
Two Loops, Two Antennas: AC Loop and DC Loop
The rectifier stage has two closed current loops, and each is an antenna whose size you set. The AC loop is the path from the AC source through the bridge and back — the loop that carries the line-frequency and the surge currents. The DC loop is the path from the bridge output through the filter and the load and back — the loop that carries the ripple and the load currents.
The antenna framing is physical. A current loop radiates in proportion to its area and the rate of change of its current; a big loop carrying fast-changing current is a better radiator than a small one. The rectifier’s switching creates exactly the fast-changing currents that radiation cares about, so the loop area is the layout’s main EMC lever. The PCB layout for rectifiers article and the EMI filter design article document the loop disciplines; this article adds the loop-shrink methods and the thermal-pad detail.
The design rule is to keep the AC loop and the DC loop as small as their physical requirements allow. The loops can overlap the same board, but their areas and the rate of current change they carry decide how much they radiate. The next section shows the concrete techniques.
Shrinking Loop Area: Trace, Via, and Component Tricks
The loop area is reduced with a handful of concrete layout tricks, and each trick attacks a different part of the loop.
First, place the rectifier and its adjacent components close together: the AC source, the bridge, and the first filter element in a tight cluster shrinks the AC loop. Second, route the outgoing and returning traces of each loop adjacent to each other, so the two conductors of the loop cancel their fields instead of spreading them; a paired, parallel run is a small antenna, while a separated run is a large one. Third, use vias where they shorten the return path — a via that drops the return trace onto the adjacent layer next to the forward trace halves the effective loop area. Fourth, put the snubber or filter element where the loop is worst, which is the subject of the snubber-placement note in the review checklist. The PCB layout for rectifiers article and the surge and EMC testing article cover the radiation and the field-cancellation logic; the habit is to inspect the board for the two conductors of each loop and ask whether they are adjacent.
The loop-shrink audit is a visual habit: walk the AC path and the DC path, find each loop’s two conductors, and measure the area between them. Every place the pair separates is a place the loop grows, and the separation is the fix target.
The loop discipline is compact enough for the cheat sheet that designers pin to the wall:
| Layout goal | The trick | What it prevents |
|---|
| Small AC loop | Tight cluster of source, bridge, filter | Surge and line radiation |
|---|
| Small DC loop | Paired forward and return traces | Ripple radiation and coupled noise |
|---|
| Short return | Via under the hot zone | Loop growth through the return path |
|---|
| Snubber at the worst loop | Place where current change is fastest | Ringing reaching the load |
|---|
| Clean ground | Split power and signal, join at one point | Sensor noise from the rectifier |
|---|
The cheat sheet is the layout review in one view: each goal names the trick and the failure it prevents, and the final checklist section runs the same five rows as a review. The PCB layout for rectifiers article and the EMI filter article provide the deeper EMC method that the cheat sheet condenses.
Thermal Pads and Via Patterns for SMD Rectifiers
For an SMD rectifier, the layout’s second job is thermal: the part sheds its heat through the solder, the pads, and the PCB copper, and the pad and via pattern set how much heat the board can move.
The thermal pad is the footprint of the rectifier’s copper land, scaled beyond the part outline so the heat spreads before it reaches the board. The via pattern is the network of plated-through holes that drop the heat to a lower copper layer or a heatsink plane; each via is a thermal short, and their count, size, and position define the vertical heat path. The discipline is to size the pad for the dissipation, place the vias directly under the hot zone, and connect them to a continuous copper area rather than a stranded one. The SMD rectifier thermal article and the TO-277 thermal guide document the pad and via math; this article applies the same discipline to the rectifier layout.
The thermal and the loop-shink goals can conflict: the thermal pad wants copper area under the part, and the loop discipline wants the return path adjacent. The resolution is the via pattern — the vias let the thermal path go down while the top-layer traces stay paired, so the board can be both cool and quiet. The layout that resolves both is the design that ships.
The thermal pad and via pattern also deserve a numerical anchor, because the sizes are what engineers argue over. The pad should extend beyond the rectifier outline by roughly the width of the part’s own thermal footprint, so the heat spreads before entering the board; the via count under the hot zone should be enough that the copper cross-section carries the dissipation without a temperature drop concentrated at the board surface. The exact numbers come from the junction-temperature calculation – ambient plus the dissipation times the thermal resistance of the pad and via column – and the same equation that sizes the rectifier’s thermal path also sizes the copper it lands on. The SMD rectifier thermal article and the rectifier thermal design guide provide the pad and via math, and the thermal management case runs the worked example.
The same calculation sets the choice between a thicker pad and more vias: the designer has two levers to collapse the surface-to-plane thermal resistance, and the one that removes the concentrated drop at the operating point is the one worth spending. The thermal pad is not decoration; it is the thermal link between the part and the board, and its size and via pattern are as much a rating decision as the rectifier’s own derating.
Power Ground vs Signal Ground: Where to Split and Join
The third layout pillar is the ground discipline: the power ground and the signal ground are not the same return, and where they split and join decides whether the signal sees the power noise.
The power ground is the return path of the rectifier currents — the ripple and the switching transients. The signal ground is the return of the control and sensing circuits. If the two share one return, the power noise rides into the signal; if they are fully isolated, the design doubles the ground structure and complicates the board. The discipline is to split the two returns but join them at a defined, single point — the classic star-point or the low-impedance reference — so the signal never crosses the power return and the grounds stay referenced. The ripple and noise diagnosis guide and the EMI filter article document the ground-noise path and its mitigation.
The split-and-join rule keeps the layout honest: split the returns near the noisy power stage, keep the signal return on its own lanes, and join them at one deliberate reference point. A board that lets the power and signal grounds mingle freely is a board whose sensor reads the rectifier — the classic symptom of a ground-discipline failure.
A Layout Review Checklist for a Small Power Board
The layout principles close with the checklist that turns them into a review, and the checklist is the practical tool a designer or a reviewer runs before the board ships.
First, walk the AC loop and the DC loop: are the two conductors of each adjacent, with the loops as small as the parts allow? Second, check the thermal pads and vias under the SMD rectifiers: is the pad sized for the dissipation, and are the vias under the hot zone and connected to continuous copper? Third, trace the power and signal grounds: are they split near the power stage and joined at one reference point? Fourth, place the snubber or filter at the worst loop — the point where the loop is largest or the current change fastest — rather than wherever it fits. Fifth, run the scope check: measure the ripple and the radiated noise at the load before and after the layout review, and confirm the improvement. The PCB layout for rectifiers article and the field reliability checklist support the five checks, and the ripple diagnosis guide covers the measurement.
The layout review closes the article. The AC loop and the DC loop are antennas whose size the designer controls; the trace, via, and component tricks shrink them; the thermal pads and vias cool the SMD parts; the power and signal grounds split and join with discipline; and the checklist verifies all five before the board leaves the bench. A rectifier stage laid out this way is quiet, cool, and predictable — the layout is the difference between a design that works on paper and one that behaves in the field. The general rectifier category supplies the parts the layout routes, and the EMI filter article completes the EMC side.