This guide is the shared reference for the thermal method used across the Good-Ark package and device articles. It explains the thermal chain, the board design levers, and the measurement discipline, so the package-specific articles can focus on their own differences instead of repeating the fundamentals. If you are new to power thermal design, read this page first.
The example values on this page are method illustrations, not product-design values. Do not use the Rth numbers or the worked figures here to finalize a design; use the selected part’s datasheet, the measured assembly data, and the package-specific articles in this series.
The Thermal Chain
Every power device’s junction temperature follows one equation:
Tj = Ta + P × Rth(j-a)
where Ta is the ambient, P is the total loss, and Rth(j-a) is the total thermal resistance from the junction to the ambient. The total resistance is a chain:
- Junction to case (Rth(j-c))—the die, die attach, lead frame, and package. This is the datasheet number and is fixed by the package design.
- Case to sink or board—the thermal interface: the solder joint, the thermal pad, the TIM, or the mounting interface. This is the designer’s first lever.
- Sink or board to ambient—the copper area, vias, inner planes, heatsink, and airflow. This is the designer’s second lever.
The chain is series: the weakest link dominates, and the datasheet Rth(j-a) is only valid for the board it was measured on.
The Board Design Levers
For surface-mount power packages, the board is half the thermal design:
| Lever | Effect | Typical practice |
|---|---|---|
| Pad size | Sets the spreading area | Extend the pad beyond the package outline |
| Copper thickness | Reduces spreading resistance | 2 oz where current and heat demand it |
| Thermal vias | Conduct heat to inner planes | Grid of plated vias under the pad |
| Inner planes | Give the heat a large area | Solid plane on an inner layer |
| Airflow | Lowers the sink-to-ambient term | Fan or enclosure design |
The lever values come from the package article for the specific package—the TO-252 article carries the DPAK footprint detail, and the QFN/DFN article the leadless pad and land-pattern detail.
The Thermal Budget Method
The standard method, used across the library:
- Compute the loss at the operating point: conduction from the hot RDS(on) or VF curve, switching from Eon/Eoff, and any leakage at temperature.
- Set the temperature budget: the target junction temperature minus the worst-case ambient.
- Derive the required Rth(j-a): budget divided by the loss.
- Design the board and sink to meet the required Rth, using the levers above.
- Measure and verify on the real assembly, with a stabilized test and a defined measurement method.
The worked examples in the TO-252 article and the junction-box article show the arithmetic in context; the method is the same everywhere.
A Worked Budget Example
Run the method with numbers: a MOSFET dissipating 5 W at full load, in an 85 °C ambient, with a 125 °C junction target.
- Budget: 125 − 85 = 40 K.
- Required Rth(j-a): 40 / 5 = 8 K/W.
- Chain check: a DPAK-class part with Rth(j-c) of 2 K/W leaves 6 K/W for the case-to-ambient path—reachable with a 2 oz pad, a via array to an inner plane, and modest airflow; tight on a minimal footprint.
- Decision: if the board cannot deliver 6 K/W, the options are a larger package, more copper, a heatsink, or a lower-loss part—the budget method identifies which lever to pull.
The numbers are example values for method. The same method applied at 150 °C targets and high ambient is the input to the high-temperature reliability article’s lifetime analysis; the thermal budget is the steady-state half, and the mission profile is the cycling half.
Transient Thermal Behavior
The steady-state Rth answers the continuous-load question; the transient thermal impedance answers the pulsed and overload questions. The Zth(j-c) curve shows how the junction temperature responds to a power pulse: a short pulse sees a much lower effective resistance than steady state, which is why pulsed ratings exceed continuous ratings. For overload events—inrush, stall, fault—the transient curve and the SOA at the starting temperature decide survival. The SOA and mission-profile articles use the same curve from different directions.
Measurement Discipline
The junction temperature is an estimate unless it is measured or modeled with care:
- Case-to-junction estimate. Case temperature plus Rth(j-c) × loss—the standard design check, with the caveat that the real Rth and loss carry error.
- TSEP. A temperature-sensitive electrical parameter calibrated against temperature—the laboratory validation method.
- Infrared thermography. Surface temperature imaging—useful for distribution, limited for the junction itself.
- Thermocouple. Contact measurement for case, heatsink, and ambient points—simple and placement-sensitive.
The high-temperature reliability article carries the full method-comparison table and the rules for measurements above 150 °C.
A measurement procedure. The repeatable sequence for a thermal verification: stabilize the system at the operating point (ambient, airflow, and load), record the case temperature and the heatsink or board temperature after equilibrium, compute the junction from Rth(j-c) and the loss, and note the instrumentation (thermocouple type, placement, and the probe for any electrical measurement). The test report’s repeatability comes from the conditions being written down—the same discipline the reliability-test section of the packaging-testing article demands.
Package Comparison at a Glance
| Package | Typical thermal path | Where the detail lives |
|---|---|---|
| TO-252 (DPAK) | Tab to PCB copper | TO-252 article |
| QFN/DFN | Exposed pad to PCB | QFN/DFN article |
| TO-220/TO-247 | Tab to heatsink | Discrete IGBT article (mounting and insulation) |
| Module | Baseplate to heatsink | IGBT and SiC articles |
Common Thermal Mistakes
The recurring failures in thermal designs follow a short list, and each has a fix:
- Using the datasheet Rth(j-a) as a constant. The value belongs to the supplier’s test board; treat it as an input to the budget, not the answer.
- Skipping the interface. The case-to-sink or case-to-board term is often the weakest link; the insulator, TIM, solder, and mounting define it.
- Designing for the average loss. The peak and the pulsed events use the transient thermal impedance and the SOA, not the steady-state Rth.
- Measuring at the wrong point. The case temperature at the tab and the heatsink temperature tell different stories; record both, and compute the junction from Rth(j-c) and the loss.
- Forgetting the ambient. The junction budget starts from the worst-case ambient inside the enclosure, not the room temperature in the lab.
The fixes are the method in this guide applied in the right order; the package-specific articles show where each mistake typically happens in their package.
Airflow and enclosure. The sink-to-ambient term is where the enclosure does its work: natural convection depends on the fin spacing and the orientation, forced airflow on the fan and the duct path, and both on the ambient inside the enclosure. A heatsink that works on the bench can fail in the sealed box; the thermal budget should use the in-enclosure ambient and airflow, and the prototype test should run with the enclosure closed. The enclosure design is part of the thermal chain, not a packaging afterthought.
Where to Go Next
- For the DPAK footprint: TO-252 (DPAK) Power MOSFETs (this series);
- For leadless packages: QFN vs DFN Packages (this series);
- For heatsink mounting: Discrete IGBT Selection (this series);
- For high-temperature and materials: High-Temperature SiC Reliability (this series);
- For the measurement method: the thermal section of the high-temperature reliability article (this series).
- For the package outlines, thermal data, and application material, the Documents section carries the datasheets and drawings; for footprint-specific support, contact Good-Ark.
The thermal numbers in every package article in this series use this guide’s method; when a package article states a temperature or an Rth result, it is an example input to the budget, not a universal value—the real numbers come from the selected part and the assembled board.
Frequently Asked Questions
Why does the datasheet Rth(j-a) not match my board? Because it was measured on the supplier’s test board with defined copper, vias, and conditions. The real value depends on your board; the budget method converts the datasheet input into a board design target, and the package articles show the measured spread for their package.
What improves thermal performance first? The weakest link in the chain. For SMT packages it is usually the case-to-board interface and the copper spreading; fix the pad, copper, and vias before adding exotic materials. For through-hole packages the interface is the insulator and the mounting pressure; the lever list changes with the package, but the method does not.
Do thermal vias really help? Yes, when they connect to an inner plane or the opposite side. Vias to nowhere add inductance and cost without removing heat; the via count, plating, and solder fill are the levers the package articles quantify.
The Method Is Reusable
Power thermal design is one method applied across packages: compute the loss, budget the temperature, derive the required Rth, design the board, and measure. Master the chain and the levers here, and the package-specific articles become details rather than new methods. The same budget feeds the reliability view in the high-temperature article, where the steady-state result becomes one input to the lifetime calculation—the thermal method and the reliability method meet at the junction temperature, and the same number serves both the heatsink design and the life prediction. Start from this guide, and every package article in the series becomes a set of specific numbers for the same method.