In a converter switching at 500 kHz or 1 MHz, the gate driver is not a peripheral—it is the timing engine. Every nanosecond of propagation delay, every ampere of peak current, and every picofarad of input capacitance shows up in the dead time, the losses, and the EMI spectrum. This article explains what “high speed” really means for a non-isolated gate driver, how to size the driver from the gate charge and target rise time, and where gallium nitride changes the rules.
What “High Speed” Means for a Gate Driver
A gate driver has four speed-related specifications, and they answer different questions:
- Propagation delay (tpd). The time from input edge to output edge. It adds directly to the control timing budget and, in a half-bridge, to the effective dead time.
- Delay matching. The difference in propagation delay between the high-side and low-side channels. In a half-bridge, the mismatch shrinks or grows the dead time asymmetrically—a 10 ns mismatch on a 50 ns dead time is 20% of the budget.
- Rise and fall time. The output edge speed, set by the peak current and the gate charge. This is the number that controls switching loss and dv/dt.
- Peak source and sink current. The driver’s ability to push charge into and pull it out of the gate. Higher current means faster edges for the same gate charge.
For a low-side or half-bridge non-isolated driver, these four numbers plus the UVLO thresholds and the input logic compatibility define the selection. The isolated-driver counterpart—with CMTI and isolation ratings—is covered in the companion gate-driver article in this series; this article stays on the non-isolated, speed-critical side.
The Gate-Charge Timing Math
The driver size follows from one equation: t = Qg / I_drive, where Qg is the total gate charge at the drive voltage and I_drive is the average current delivered over the switching interval. The table shows the current needed for representative gate charges and target rise times; it is an example calculation, and real edges are slower than the ideal because the driver output impedance and the gate resistance add time:
| Gate charge Qg | 10 ns target | 25 ns target | 50 ns target |
|---|---|---|---|
| 10 nC | 1.0 A | 0.4 A | 0.2 A |
| 30 nC | 3.0 A | 1.2 A | 0.6 A |
| 60 nC | 6.0 A | 2.4 A | 1.2 A |
| 120 nC | 12 A | 4.8 A | 2.4 A |
The second lever is the gate resistance: it deliberately slows the edge to control dv/dt and EMI. The driver’s peak current sets the fastest possible edge; the gate resistor sets the actual one. In practice, the design picks the edge speed for the EMI and ringing budget, then verifies the driver can deliver the required current through the chosen resistor.
Where GaN Changes the Rules
Gallium nitride (GaN) transistors switch far faster than silicon MOSFETs, and they change the driver requirements:
- Lower gate charge. GaN’s gate charge is small (often single-digit nanocoulombs), so the current demand is low—but the edges are so fast that the driver’s own delay and jitter dominate the timing.
- No body diode. GaN has no PN body diode; reverse conduction happens through the channel at a higher drop, so dead-time control is more critical and the drive timing must be tight.
- Tight voltage window. The recommended gate voltage range is narrow, and the maximum is low; the driver’s UVLO and output regulation must hold the gate inside the window. Some GaN parts integrate the drive, in which case the “driver” selection becomes a transistor selection.
- Package and loop inductance. At sub-nanosecond edges, the gate-loop inductance—driver output, gate resistor, transistor gate, and source return—sets the ringing. The driver’s package and the layout matter as much as the datasheet numbers.
The practical consequence: for GaN, choose the driver for low propagation delay, tight matching, and a clean output stage, then design the gate loop as a transmission-line discipline rather than a wire.
Two GaN-specific details deserve their own attention. First, gate overshoot: the recommended gate-voltage window is narrow and the maximum is low, so ringing on the gate edge can exceed the rating even when the steady-state drive is correct. The gate resistor, the loop inductance, and the driver’s output impedance set the overshoot; verify it on the real edge, not in the spreadsheet. Second, the source-return path: GaN parts with a separate Kelvin source connection keep the gate loop out of the power loop, reducing the common-source inductance that couples power transients into the gate. A Kelvin-source part only pays off if the layout actually separates the gate return from the power current path.
What Transfers From MOSFET Design—and What Does Not
The low-voltage silicon MOSFET driver world and the GaN driver world share the gate-charge arithmetic: the current required for a target rise time is Qg / t in both, and the dead-time budget method is the same. The differences are where the design mistakes happen:
| Design step | Low-voltage MOSFET | GaN |
|---|---|---|
| Gate voltage window | Wide (10–20 V, tolerant) | Narrow, low maximum; overshoot matters |
| Reverse conduction | Body diode at fixed drop | Channel conduction, higher drop, dead-time sensitive |
| Miller clamping | Helpful | More critical; negative drive often replaced by Miller clamp |
| Source return | Shared source acceptable at low frequency | Kelvin source and separated loop recommended |
| Driver speed | 10–100 ns edges | Sub-10 ns edges; delay and jitter dominate |
The table is a heuristic for the design review, not a universal rule—specific parts and layouts shift the boundaries. The transferable skills are the timing budget, the loop discipline, and the measurement method; the non-transferable details are the gate window, the reverse conduction, and the package parasitics.
Split source and sink resistors. Separating the turn-on and turn-off paths with individual resistors is a standard technique in fast bridges: a slower turn-on limits dv/dt and EMI, while a fast turn-off controls the commutation and reduces shoot-through risk. The Miller clamp serves a related role by holding the gate low during the opposite switch’s fast edge, preventing parasitic turn-on; check that the driver offers the clamp and that the clamp path is low-inductance.
Layout for Speed
The fastest driver in the catalog is useless with a long gate trace:
- Minimize the gate loop. The driver output, gate resistor, device gate, and source return form one loop; keep it as small as the layout allows.
- Place the bypass capacitors at the driver pins. The local decoupling supplies the transient current; a capacitor a few centimeters away is electrically absent at the switching edge.
- Separate power and signal returns. The high-current path must not share the driver’s quiet ground.
- Use a low-inductance package for the driver where the switching frequency demands it, and match the driver’s output impedance to the gate path.
- Measure the real edge. Probe the gate-source voltage with a low-inductance probe; the measured rise time and ringing are the acceptance criteria, not the datasheet’s typical value.
For the driver and low-voltage power device families available, the product catalog on the Good-Ark site is the entry point, and the contact page connects you to the team for part-level selection.
A Selection Checklist for High-Speed Drivers
- Calculate the required current from Qg and the target rise time; add margin for the gate resistor and driver impedance.
- Check the propagation delay and matching against the dead-time budget and the control timing.
- Verify the output voltage and UVLO against the device’s gate window—especially for GaN’s narrow range.
- Confirm the input logic compatibility and any enable/disable or interlock features for the topology.
- Match the driver package to the layout’s loop-inductance budget.
- Prototype and measure the gate edge, dead time, and EMI on the real board.
Dead-Time, Shoot-Through, and the Timing Budget
In a half-bridge, the driver’s speed specifications translate directly into two failure risks, and the arithmetic is worth doing before the schematic is drawn.
Shoot-through. If the high-side and low-side drivers are both on—even for tens of nanoseconds—the input capacitors short through the bridge, with destructive current. The protection is dead time: a deliberate interval with both switches off between transitions. The driver’s propagation delay and channel matching eat into that interval from both ends. With a 50 ns programmed dead time, a 15 ns propagation delay on each channel and a 10 ns mismatch leave only about 10 ns of real off-time—inside the ringing uncertainty of a fast layout.
Body-diode and reverse conduction loss. During the dead time, the current flows through the device’s reverse path—the body diode of a silicon MOSFET or the channel of a GaN device. Every nanosecond of unnecessary dead time adds conduction loss and, in the synchronous-rectifier context, hurts efficiency. The driver’s job is to make the dead time as short as the shoot-through risk allows; the delay matching is what makes that possible.
The timing budget method: sum the controller’s resolution, the driver’s propagation delay and matching, the gate-resistor RC, and the device’s switching time; compare the total against the dead-time window. If the budget exceeds the window, either the driver is too slow, the gate loop too sluggish, or the dead time too short—and the fix is identified before the first prototype. The companion article on synchronous rectifier MOSFETs in this series covers the dead-time loss side of the same equation from the device’s perspective.
Frequently Asked Questions
What is the difference between rise time and propagation delay? Propagation delay is the time from the input edge to the output starting to move—it adds directly to the control timing and dead-time budget. Rise time is the time the output takes to complete the transition—it sets the switching loss and dv/dt. A driver can be fast in one and slow in the other, so check both.
How do I choose between a driver and an integrated GaN half-bridge? Integrated GaN devices embed the driver for the optimal gate loop; discrete drivers suit designs with custom drive needs or mixed devices. The decision is about loop control and flexibility.
Does a higher peak-current driver always switch faster? Only up to the limit set by the gate resistance and the loop inductance. Beyond that, the edge is set by the resistor and layout; a bigger driver adds cost without speed.
Why does gate overshoot matter so much with GaN? The maximum gate voltage is low and the recommended range is narrow, so ringing on the edge can exceed the rating even when the steady-state drive is correct. The gate resistor and the loop inductance set the overshoot; verify it on the measured waveform.
The Timing Engine
A high-speed gate driver is selected by arithmetic—Qg over the target rise time—and finished by layout. Size the current, verify the delay and matching against the dead-time budget, respect the device’s gate window, and treat the gate loop as a controlled transmission line. At high frequency, the driver is not a component; it is the timing engine that decides whether the converter reaches its efficiency and EMI targets. To review gate-drive requirements for high-frequency switching stages, start from the product catalog and contact Good-Ark with your device and target edge.
FAE note before publication: add a measured gate waveform (VGS edge, overshoot, dead-time interval) for a representative GaN half-bridge layout, with the probe and bandwidth noted.