The gate driver sits between the control domain and the power stage, and in high-voltage systems it does two jobs at once: it amplifies the controller’s signal into a strong, fast gate pulse, and it isolates the low-voltage control side from a floating, potentially lethal power rail. Choose the wrong driver and the system fails in subtle ways—shoot-through, parasitic turn-on, false faults, or emissions that fail compliance. This article explains the parameters that matter when selecting an isolated gate driver for SiC and IGBT stages, from common-mode transient immunity to isolation ratings.
Why Isolation Is Non-Negotiable at High Voltage
In a half-bridge or inverter stage, the high-side switch’s source rides on a voltage that swings by hundreds of volts at switching frequency. The controller, on the other side, references ground. A gate driver with galvanic isolation lets the controller communicate across that boundary safely, while also protecting the low-voltage electronics from fault transients.
The isolation barrier also suppresses the ground noise that otherwise couples from the power stage into the control electronics—the same noise that corrupts measurements and causes false logic states. In motor drives, solar inverters, and EV chargers, isolation is both a safety requirement and an electromagnetic compatibility (EMC) requirement.
The Parameters That Decide the Selection
Common-mode transient immunity (CMTI). This is the driver’s ability to reject fast voltage swings across the isolation barrier without corrupting the output. When a SiC MOSFET switches at hundreds of volts per nanosecond, the coupling capacitance across the barrier injects displacement current into the receiver; if the receiver is not immune, the output glitches and the power switch mis-triggers. High-CMTI drivers (100 kV/µs class) are specified for SiC systems for exactly this reason.
Propagation delay and delay matching. The delay from input to output sets the timing accuracy of the whole stage. In half-bridge designs, the mismatch between the high-side and low-side channels determines the effective dead time: if one channel responds faster than the other, the dead time shrinks and shoot-through risk rises. Compare the maximum, not typical, delay values, and the channel-to-channel matching specification.
Peak source and sink current. The driver must deliver the gate charge fast enough to switch the device within the target time. A 1200 V SiC MOSFET with 100–200 nC of gate charge needs a driver capable of several amperes of peak current; IGBTs with larger gate charge may need more. The source current charges the gate (turn-on), the sink current discharges it (turn-off), and asymmetric ratings are common—turn-off often needs more current for fast, controlled commutation.
Output voltage swing and UVLO. The driver’s output high level must match the power device’s recommended gate voltage: typically +15 V for IGBTs and +18 to +20 V for SiC MOSFETs, with a negative off-state voltage (−2 to −5 V) for SiC to prevent parasitic turn-on. The under-voltage lockout (UVLO) thresholds define when the driver refuses to operate; they must align with the device’s gate-drive window so the switch never runs partially on.
Isolation rating and creepage. The driver’s isolation voltage, working voltage, and creepage/clearance determine both safety and reliability. Reinforced isolation is required in many applications (mains-connected power supplies, EV chargers, medical), and the package’s creepage distance must match the pollution degree and operating voltage of the design. Confirm the safety standard certificates (for example IEC 60747-17 for capacitive isolators) and the datasheet’s isolation ratings.
Matching the Driver to the Power Device
The driver and the switch must be designed as a pair. The table below compresses the device-level differences into driver requirements; the full device-selection logic for each switch is covered by the companion articles on SiC MOSFETs and IGBTs in this series.
| Drive requirement | IGBT | SiC MOSFET |
|---|---|---|
| Recommended VGS(on) | +15 V | +18 to +20 V |
| Off-state VGS | −5 to −15 V | −2 to −5 V |
| UVLO alignment | 15 V window | Higher window; check against the SiC turn-on voltage |
| Gate charge scale | Larger, often 200 nC+ | 50–200 nC typical, fast edges |
| CMTI need | Moderate (10–50 kV/µs) | High (100 kV/µs class) |
| Protection typical | DESAT + soft turn-off | DESAT where applicable, Miller clamp, negative drive |
With the device requirement fixed, work through the pairing steps:
- Start from the gate charge (Qg). Estimate the required peak current from the target switching time: I = Qg / t. A 100 nC gate charged in 100 ns needs 1 A average over that window, with higher peaks in practice.
- Choose the gate voltage rails from the power device’s datasheet, then confirm the driver’s output stage and UVLO cover them.
- Size the gate resistor to control dv/dt and ringing. The driver’s peak current sets the minimum resistance; the layout’s inductance sets the practical limit.
- Check the protection features: desaturation (DESAT) sensing for IGBTs, Miller clamping, soft turn-off, and fault feedback are the features that turn a driver into a protection system.
- Verify the timing budget end to end: controller delay, driver propagation delay, gate resistor RC, and device switching time must fit the dead-time and frequency plan.
The gate driver is often the component where the difference between a stable design and a field failure is decided. The product catalog provides the family overview, and the datasheets carry the isolation rating table and certificate claims.
A Layout Checklist for Isolated Gate Drivers
The datasheet’s performance is only as good as the board around it. A practical layout checklist for the driver and its power device:
- Keep the gate loop small. The driver output, gate resistor, MOSFET gate, and source return must form the tightest possible loop. Long gate traces add inductance that rings with the gate capacitance and can trigger false turn-on.
- Place the bypass capacitors close to the driver’s supply pins. The local decoupling supplies the transient gate current; a capacitor a few centimeters away is electrically useless at the switching edge.
- Separate the power ground from the signal ground. The high-current return path must not share the driver’s quiet ground. Use a star or a dedicated return so the control signals do not see the power-stage voltage drop.
- Route the sense and feedback traces away from the gate trace. Desaturation sense and fault lines are susceptible to coupled dv/dt; shielding or spacing reduces false faults.
- Follow the isolation creepage rules. The PCB must respect the clearance and creepage required for the working voltage—the driver’s package creepage alone is not enough; the board’s solder mask and slotting define the real path.
- Measure the waveforms on the actual board. Probe the gate-source voltage during hard switching with a low-inductance probe; the ringing amplitude and the turn-on/turn-off times are the acceptance criteria.
The fault-handling flow. A modern isolated driver with protection turns a failure event into a controlled sequence: the DESAT or overcurrent detector trips, the driver pulls the gate low with a controlled soft turn-off (to avoid an inductive overvoltage), reports the fault to the controller through the isolation barrier, and the controller decides the retry or shutdown policy. Verify the entire flow in the lab with an injected fault—the response time, the collector overshoot, and the fault reset behavior—because the paper specification and the measured behavior can differ by a wide margin.
Safety Standards and Compliance Documents
For mains-connected and high-voltage systems, the driver’s isolation rating must be documented against recognized standards:
- IEC 60747-17 covers capacitive isolation components (the basis for many modern isolated drivers);
- UL 1577 certifies the isolation barrier’s withstand voltage;
- IEC/UL 62368-1 applies to the end equipment for mains-powered products;
- IEC 61800-5-1 and IEC 61508 families apply in drive and functional-safety contexts.
When qualifying a driver, request the certificate and the datasheet’s isolation rating table, and confirm the working voltage, transient overvoltage, and creepage values against the end-equipment standard. A driver without the right certificate can force a redesign late in the compliance phase.
Standards referenced. IEC 60747-17 covers magnetic and capacitive isolation couplers; UL 1577 is the safety standard for optical isolators and related components; IEC/UL 62368-1 governs mains-connected end equipment; IEC 61800-5-1 covers adjustable-speed drives and the IEC 61508 family the functional-safety context. Editions and applicability depend on the target market and product category—verify the current revision and scope at the standards bodies (iec.ch, ul.com) before finalizing the certificate matrix.
Selection Matrix: Gate Charge to Driver Current, dv/dt to CMTI
Two quick tables translate the power device’s requirements into driver numbers.
Step 1: gate charge → peak current. The target switching time sets the required drive current: I = Qg / t. The table shows the current for representative gate charges and switching times; it is an illustrative calculation, and real designs add margin for gate resistance and driver output impedance.
| Gate charge Qg | 50 ns target | 100 ns target | 200 ns target |
|---|---|---|---|
| 50 nC | 1.0 A | 0.5 A | 0.25 A |
| 100 nC | 2.0 A | 1.0 A | 0.5 A |
| 200 nC | 4.0 A | 2.0 A | 1.0 A |
| 400 nC | 8.0 A | 4.0 A | 2.0 A |
Step 2: dv/dt → CMTI margin. The driver’s common-mode transient immunity should comfortably exceed the actual dv/dt at the power device’s drain, because the coupled displacement current scales with the parasitic capacitance across the isolation barrier. A common rule of thumb is to select a driver whose CMTI is at least twice the expected dv/dt; a 150 V/ns SiC edge then points to the 100 kV/µs class rather than a 50 kV/µs part.
Step 3: close the loop with delay and protection. With the current and CMTI fixed, compare propagation delay and channel-to-channel matching against the dead-time budget, and confirm the protection set (DESAT, Miller clamp, soft turn-off, fault feedback) matches the power device and the fault philosophy of the system. These three steps produce a shortlist; the layout checklist below then decides the winner.
Frequently Asked Questions
Why do SiC MOSFETs need a driver with high CMTI? SiC switches much faster than silicon, creating extremely high dv/dt across the isolation barrier. High CMTI prevents that transient from coupling through the barrier and glitching the gate signal, which would otherwise cause parasitic turn-on or false faults.
Can I use an IGBT driver for a SiC MOSFET? Sometimes, but check the output voltage (SiC needs higher turn-on voltage), the UVLO thresholds, the CMTI, and the negative off-state capability. A driver designed for IGBTs may not cover the SiC gate-drive window safely.
What does “reinforced isolation” mean for a gate driver? It is an isolation class defined by safety standards, providing protection equivalent to double insulation for end-user accessible equipment. The driver’s certificate and datasheet state the working voltage and transient ratings under that class.
How much peak current do I need? Estimate from the gate charge and target switching time. A 100 nC gate switched in 100 ns needs roughly 1 A average peak capability; larger IGBTs or faster targets need more. Confirm the driver’s source and sink peaks separately.
Where can I check Good-Ark gate driver documentation? The product catalog covers the driver and power-device families, and the datasheets carry the isolation rating table and certificate claims. For design support, contact Good-Ark.
The Driver Pairing Rule
The isolated gate driver is selected in three steps: match the peak current to the gate charge and target switching time, match the CMTI to the device’s dv/dt with margin, and close the loop with delay, protection, and certificate checks. Work through the two tables, verify the isolation documents against the end-equipment standard, and the barrier between control and power becomes a reliable asset instead of a failure point. The device-side context for the pairing comes from the companion SiC MOSFET and IGBT articles in this series, and the product catalog with the contact page complete the sourcing path.