This guide is the shared reference for gate-drive design across the Good-Ark library. It covers the two questions every drive design answers—how much current, and how much dead time—plus the protection set, and it routes the device-specific detail to the dedicated articles. Read this page for the method; read the linked articles for the device context.
Sizing the Driver: The Qg Math
The driver’s size follows from the gate charge and the target edge:
I_drive = Qg / t
The required current for representative gate charges and rise times is tabulated in the GaN gate-driver article; the method is the same for every device. Two refinements matter in practice:
- The gate resistor sets the real edge. The driver’s peak current defines the fastest possible transition; the resistor defines the actual one, balancing switching loss against EMI.
- The gate-drive power is Qg × VGS × fsw. The driver and its supply must deliver this average power; a larger die demands more, and the practical frequency falls when the drive budget is small.
Timing and Dead Time
In a half-bridge, the driver’s propagation delay and channel matching eat into the dead-time window from both ends:
- Propagation delay adds directly to the control timing;
- Delay matching between the high-side and low-side channels shrinks or grows the dead time asymmetrically;
- The dead-time budget is the sum of the controller resolution, the driver delays, the gate-resistor RC, and the device switching time—and it must fit inside the window that prevents shoot-through while minimizing reverse-conduction loss.
The full budget method and the shoot-through arithmetic are in the GaN gate-driver article; the dead-time loss side is covered from the device’s perspective in the synchronous rectifier article.
A Worked Timing Example
Run the dead-time budget with numbers for a half-bridge switching at 500 kHz: a programmed dead time of 100 ns, a driver with 20 ns propagation delay per channel and 8 ns matching, a gate-resistor RC of 15 ns, and a device switching time of 30 ns.
- Worst-case delays: 20 + 8 = 28 ns of driver delay on the late channel, plus 15 ns RC and 30 ns switching—about 73 ns consumed from one end.
- Both ends: roughly 73 ns worst case against a 100 ns window leaves about 27 ns of real off-time—inside the ringing uncertainty of a fast layout, and a warning sign.
- Decision: either a faster driver (lower delay and matching), a smaller gate resistor, or a longer programmed dead time with its reverse-conduction loss—the budget identifies the levers before the prototype.
The values are example inputs for method. The same arithmetic, run with the actual driver and device data, is the standard pre-schematic check for shoot-through risk.
The Qg sizing in numbers. For a 100 nC gate switched in 50 ns, the driver needs 2 A average; with the gate resistor and output impedance, a 4 A peak driver is the practical choice. The sizing table in the GaN article carries the full matrix; the arithmetic is the same for every device family.
Protection: The Standard Set
The protection features turn a driver into a protection system:
| Feature | What it does | When it matters |
|---|---|---|
| UVLO | Holds the output off until the supply is valid | Every drive; thresholds must match the device window |
| Desaturation (DESAT) | Detects overcurrent and initiates turn-off | IGBTs and fault-prone stages |
| Miller clamp | Holds the gate low during the opposite edge | Fast bridges and SiC |
| Soft turn-off | Controls the turn-off edge during faults | Inductive loads; prevents overvoltage |
| Fault feedback | Reports the event across the isolation barrier | System protection logic |
The IGBT articles carry the DESAT and active-clamp detail; the SiC articles carry the negative off-state and CMTI context; the isolated-driver article carries the isolation ratings and certificates.
Isolated or Not?
The isolation decision is the first fork in the drive design:
- Non-isolated drivers serve low-side and half-bridge stages where the control and the power share a reference; the GaN gate-driver article covers the high-speed, non-isolated case.
- Isolated drivers are required for high-side floating stages, high-voltage systems, and safety-relevant isolation; the isolated gate-driver article covers CMTI, delay, isolation class, and certification.
The isolation class—functional, basic, or reinforced—comes from the end-equipment standard, not the driver’s preference.
A protection scenario walk-through. Consider a motor-drive IGBT with a DESAT-protected driver: the IGBT enters desaturation during a load fault, the driver’s DESAT comparator detects the rising collector voltage after the blanking time, the soft turn-off controls the edge to avoid an inductive overvoltage, and the fault is reported across the isolation barrier to the controller, which decides the retry policy. Each step has a specification—the blanking time, the soft-turn-off current, the fault response delay—and the whole flow should be verified in the lab with an injected fault, because the measured response can differ from the paper values by a wide margin. The IGBT articles carry the device-side detail; the isolated-driver article carries the isolation-side ratings.
The supply design. The gate-drive supply must deliver the average power Qg × VGS × fsw plus the driver quiescent, and hold the rail through the peak edges. The isolated DC-DC module article carries the sizing method; a rail that sags below the UVLO during switching is one of the most common drive failures.
The Device-Specific Windows
Each power device family has a gate-drive window that the driver must honor:
| Device | Typical VGS(on) | Off-state | Where the detail lives |
|---|---|---|---|
| Low-voltage MOSFET | 10 V (or logic level) | 0 V | N/P and logic-level articles |
| Super junction MOSFET | 10 V | 0 V | Super junction article |
| IGBT | 15 V | −5 to −15 V | IGBT articles |
| SiC MOSFET | 18–20 V | −2 to −5 V | SiC articles |
| GaN | Narrow, low maximum | 0 V | GaN gate-driver article |
The table is a screening summary; the exact window comes from the device datasheet and the driver’s UVLO and output stage must match it.
The supply and decoupling discipline. The gate-drive rail is a transient load: each switching edge draws a current burst, and the rail must hold through it. The local decoupling capacitors at the driver supply pins supply the burst; a capacitor a few centimeters away is electrically absent at the edge. The supply design—module or discrete—must deliver the average power and tolerate the peak; the isolated DC-DC module article carries the sizing, and the GaN article carries the layout discipline. A rail that dips toward the UVLO threshold during switching is one of the most common drive failures, and it is a supply-and-layout problem, not a driver-selection problem.
Verify with the waveform. The acceptance criteria are measured, not assumed: the gate-source waveform at full load shows the edge, the overshoot, and the dead-time interval; the drain waveform shows the ringing and the spike. The GaN article’s measurement section and the 1700 V article’s VDS-peak method describe the probing discipline; every drive design in this series ends at the same point—the measured waveform on the real board.
A driver selection matrix. The three drive decisions compress into a short matrix: the peak current from Qg over the target rise time, the delay and matching against the dead-time budget, and the protection set against the fault profile. The isolated decision adds the CMTI and the isolation class. The matrix’s rows are the specifications to compare across candidates; the columns in the GaN and isolated-driver articles carry the numbers.
Where to Go Next
- For the high-speed, non-isolated case: High-Speed Gate Driver Design for GaN Half-Bridges (this series);
- For the isolated case: Isolated Gate Drivers for SiC and IGBT Bridges (this series);
- For the device context: the SiC, IGBT, and synchronous rectifier articles (this series);
- For the driver and device families, the product catalog is the entry point; for project support, contact Good-Ark.
Frequently Asked Questions
How do I know what peak current the driver needs? Divide the gate charge by the target rise time, then add margin for the gate resistor and the driver’s output impedance. The sizing table in the GaN gate-driver article shows the arithmetic.
What is the difference between delay and rise time? Propagation delay is the time from the input edge to the output starting to move; rise time is the transition duration. Delay adds to the timing budget; rise time sets the loss and dv/dt.
Do I need an isolated driver for every high-side switch? Only when the control and the switch cannot share a reference—floating high-side stages and high-voltage systems. Non-isolated drivers with bootstrap or charge-pump supplies cover many low-voltage half-bridges.
What is the most common gate-drive field failure? A recurring cause seen in field-return studies and FAE experience is the rail sagging toward the UVLO threshold during a switching burst, typically from undersized supply or decoupling rather than from the driver itself. Confirm the mechanism with your own fault data before generalizing; the supply and layout discipline in this guide is the prevention.
The Drive Is the Timing Engine
Gate-drive design is three calculations—current from Qg, dead time from the delays, and the protection set from the faults—plus one decision, isolation. Work the sizing and timing here, follow the device windows in the linked articles, verify the supply and the waveform, and the drive becomes a controlled asset instead of a source of field failures.