The jump from 1200 V to 1700 V changes more than the voltage rating on the datasheet. A 1700 V device exists because the system around it operates at 1500 V DC—utility-scale solar arrays, battery storage, and some rail traction—where the margin arithmetic leaves little room for error. This article explains where the 1700 V class fits, how the topology and derating decisions interact, and why insulation and creepage become first-order design problems at this voltage.
Why the 1700 V Class Exists
Two system voltages drive the class:
- 1500 V DC solar. Utility-scale and large C&I arrays standardize on 1500 V to reduce cabling and string losses. A 1200 V device cannot block the 1500 V bus with any honest margin, so the choice is a 1700 V device or a different topology.
- Rail and traction. Auxiliary power and some traction converters operate on DC link voltages around 1500 V, with a long history of 1700 V IGBT modules; SiC MOSFETs enter where efficiency and frequency targets exceed what the IGBT delivers.
The 1700 V SiC MOSFET brings the same toolset as its 1200 V sibling—fast switching, recovery-free body diode, stable hot RDS(on)—to a voltage class where silicon IGBTs and diodes have held the field. The design questions, however, shift from “which device” to “which topology and which insulation system.”
Topology First: 2-Level, 3-Level, or 1700 V
The 1500 V bus can be handled three ways, and the choice changes the device count, the loss, and the cost:
| Approach | Devices per phase | Drives per phase | Typical use | Key trade-off |
|---|---|---|---|---|
| 2-level with 1700 V devices | 1 switch position | 1 | Rail auxiliary, some solar | Simple control; device voltage margin tight at 1500 V |
| 3-level NPC with 1200 V devices | 4 switches | 4 | Utility solar inverters | Each device blocks half the bus; more parts, drives, and control complexity |
| 3-level T-type with 1200 V devices | 2 switches plus bidirectional pair | 2–4 | Utility solar inverters | Fewer switches than NPC; device stress and freewheeling path differ |
| 2-level with higher-voltage module | 1 module (1700 V or 3300 V class) | 1 | High-power central inverters, traction | Fewer devices; module-level insulation and thermal design |
The 3-level approach was the standard workaround when 1700 V silicon had poor switching performance. The 1700 V SiC MOSFET changes the arithmetic: a simple 2-level stage with fast switching can beat a 3-level stage in loss and component count at high frequency. The right answer depends on the power level, the switching frequency target, and the module packaging available—there is no universal winner.
Derating at 1700 V: The Margin Arithmetic
Voltage derating is a safety margin between the worst-case voltage the device sees and its rating. At 1500 V DC, the numbers get uncomfortable:
- Nominal bus: 1500 V DC, leaving only 200 V of headroom on a 1700 V device before any transient.
- Switching spikes: the parasitic inductance of the commutation loop adds overshoot at turn-off; the layout must keep this inside the margin.
- Surge and fault: line transients, load steps, and fault events can push the bus above nominal; the protection and clamping strategy defines the real worst case.
- Altitude and temperature: insulation and blocking capability degrade with altitude and high temperature; the derating curves in the datasheet and the insulation standards must be applied.
Keep four voltages distinct in the budget: the nominal DC-link voltage, the maximum continuous DC-link voltage (including the cold-temperature open-circuit rise of a solar array), the maximum surge the protection network allows, and the peak switching overshoot. The device rating must clear the sum of the surge and overshoot terms with margin; conflating them is how a 1500 V design ends up with a 1700 V part running at its limit.
The practical rule at 1500 V: design the commutation loop for minimal inductance, clamp the worst-case transient, and verify the margin with a real measurement of the peak voltage at the device—on the production-representative board, not the ideal schematic. The same discipline at 1200 V is covered in the companion article on 1200 V SiC MOSFETs in this series; at 1700 V there is simply less room to be sloppy.
Insulation and Creepage Become First-Order Problems
At 1500 V DC, the device rating is only part of the insulation system. The PCB, the module, and the system must all handle the working voltage:
- Creepage and clearance. The distance along and across the insulating surface must satisfy the applicable standard—IEC 62109 for solar inverters, UL 1741 for grid-connected equipment, and EN 50124-1 for rail applications. Pollution degree, material group, and altitude modify the required distances.
- PCB materials. The insulation resistance and tracking resistance of the board material matter at 1500 V; conformal coating and slotting are common techniques for keeping creepage within the board area.
- Module insulation. The module’s isolation voltage, the internal materials, and the creepage between terminals decide whether the module itself is rated for the system voltage.
- Partial discharge. High-voltage power electronics at high dv/dt can generate partial discharge inside the module and the PCB; the design should respect the partial-discharge-inception voltage margins rather than only the breakdown voltage.
The qualification documents for the device and the module must state the isolation and creepage ratings; verify them against the end-equipment standard before design-in. Standards such as IEC 62109 and UL 1741 have specific insulation requirements for PV equipment, and the current editions should be checked at the standards bodies (iec.ch, ul.com).
Pollution degree, material group, and altitude are first-order inputs to the creepage calculation, not footnotes: the required distances change with each. Standards applicability depends on equipment category, installation environment, regional certification route, insulation class, pollution degree, and system architecture. This article is not a compliance determination; the numerical creepage and clearance values for a specific design must come from the applicable standard edition and the equipment’s defined conditions.
Gate Drive and Protection at 1700 V
The 1700 V SiC gate drive follows the same rules as 1200 V—+18 to +20 V turn-on, negative off-state, high CMTI—with two additional pressures:
- dv/dt stress. The faster the edge, the more stress on the insulation and the greater the common-mode current through the module’s parasitic capacitance. The gate resistor is the lever that balances switching loss against dv/dt and EMI.
- Fault handling. At 1500 V, a short circuit delivers enormous energy; the protection must act within the device’s short-circuit withstand time, and the soft turn-off must prevent inductive overvoltage on the already tight margin.
The isolated driver selection—CMTI, delay, and isolation ratings—is covered in the companion gate-driver article in this series; the PV inverter application section of the Good-Ark site groups the SiC families used in these stages.
A Decision Checklist for 1700 V Designs
- Choose the topology (2-level vs 3-level) before the device; simulate the loss and component count at your power and frequency.
- Set the derating budget: nominal bus, worst-case transient, clamp level, and altitude/temperature derating.
- Design the commutation loop for low inductance and measure the peak voltage on the real board.
- Verify the insulation system against the applicable standard—creepage, clearance, partial discharge, and module ratings.
- Design the gate drive and protection for the SiC window and the fault energy.
- Confirm documentation and supply with the manufacturer before design-in.
A 1500V Solar Stage in Numbers
To make the margin arithmetic concrete, consider a utility-scale string inverter operating on a 1500 V DC bus with a 1700 V SiC MOSFET in a 2-level stage. The exercise is an example, but the method is the design:
- Nominal margin. 1700 V minus 1500 V leaves 200 V for everything else—switching overshoot, line transients, and measurement tolerance. That is tight by power-electronics standards.
- Switching overshoot. The turn-off spike depends on the commutation-loop inductance and the turn-off di/dt. With a 50 nH loop and 200 A/µs, the spike is 10 V; with 200 nH and 1000 A/µs, it is 200 V—the entire margin. The layout, not the device, decides whether the design survives.
- Line and fault transients. The protection and clamping strategy defines the worst-case bus: a clamp that holds the bus at 1550 V leaves 150 V for the switching spike; no clamp leaves the fault transient to the device.
- Altitude and temperature. At 3000 m altitude, the insulation strength is reduced and the standard’s altitude correction applies; at high junction temperature, the blocking margin can also be affected. Both corrections subtract from the already tight budget.
The conclusion is practical: a 1700 V design at 1500 V nominal is an inductance-management problem as much as a device-selection problem. The layout and the clamp define the real margin; the datasheet rating is only the envelope.
Measuring the peak voltage. The margin arithmetic is only as good as the measurement: probe the drain-source voltage at the device with a differential or isolated probe rated for the voltage, a bandwidth well above the switching harmonics, and a ground lead short enough to avoid pickup. A long ground lead adds inductance that rings with the probe capacitance and shows a false spike; the number that counts is the peak measured on the production-representative layout.
Rail context. Traction and rail auxiliary systems add their own rules: EN 50124-1 governs insulation coordination, the DC-link voltage classes and surge profiles come from the rail standards, and the mission profile includes vibration and a much harsher thermal cycle. The 1700 V SiC MOSFET’s fast switching and high-temperature margin matter in the same way as in solar, but the qualification evidence and the insulation calculation must follow the rail route rather than the PV one.
Frequently Asked Questions
Why not just use 1200 V parts on a 1500 V bus? 1200 V leaves no honest margin at 1500 V nominal. The options are 1700 V devices or a 3-level topology that splits the bus voltage across 1200 V devices.
Is a 3-level topology still better than a 2-level with 1700 V SiC? It depends. 3-level reduces the per-device voltage but adds devices and control complexity; 1700 V SiC makes a simple 2-level stage competitive at high frequency. Simulate both at your power level.
What standards govern insulation at 1500 V solar? IEC 62109 (safety of power converters for PV systems) and UL 1741 (inverters and converters for grid-connected PV) define the insulation and clearance requirements; rail applications use EN 50124-1. Verify the current editions and their scope.
Does altitude really matter for 1700 V devices? Yes. Insulation strength and blocking capability degrade with altitude because of lower air density; the derating curves and the standard’s altitude corrections must be applied.
The System Around the Device
At 1700 V, the device is the least forgiving part of a system that is already unforgiving. Choose the topology deliberately, keep the derating honest, and treat insulation as a first-order engineering task. The 1700 V SiC MOSFET’s fast switching and clean body diode only pay off when the margin arithmetic and the insulation system around it are designed with the same care. To review 1700 V SiC options for 1500 V DC-link designs, start from the PV inverter application section and request the family data, module insulation ratings, and qualification documents from the Good-Ark team.
FAE note before publication: add the measured VDS peak waveform and overshoot budget for a representative 1500 V layout, and the module insulation rating table with the applicable standard edition.